TAS2780 datasheet(29/97 Pages) TI

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To prevent the damage the OCP limit needs to be adjusted based on VBAT1S level measured by the internal

SAR ADC. The table below presents the thresholds where the OCP will be adjusted and the settings of the

registers to program these thresholds.

Once the VBAT1S supply is detected to a level below 3.4 V the device needs to be put in software shutdown or

in idle mode before programming the registers.

Table 8-4. OCP Thresholds vs VBAT

VBAT1S Range

PVDD OCP Level

Book/Page/Register - New Setting

VBAT1S ≥ 3.4 V

6.6 A

3.1 V ≤ VBAT1S < 3.4 V

6 A

B_0/P_0/R_6 - 01

2.9 V ≤ VBAT1S < 3.1 V

5.3 A

B_0/P_0/R_6 - 02

2.7 V ≤ VBAT1S < 2.9 V

4.3 A

B_0/P_FD/R_3A - 7D

B_0/P_FD/R_3B - See Section 10.6

B_0/P_FD/R_5C - C0

The control of OCP threshold from above is needed only in power modes where VBAT1S is supplied externaly

and the Class-D outputs are switching on PVDD (PWR_MODE0, PWR_MODE1).

8.4.10 Clocks and PLL

The device clocking is derived from the SBCLK input clock. Table 8-5 and Table 8-6 show the valid SBCLK clock

frequencies for each sample rate and SBCLK to FSYNC ratios.

Table 8-5. Supported SBCLK Frequencies (48 kHz based sample rates)

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

125

48 kHz

768 kHz

1.152 MHz

1.536 MHz

2.304 MHz

3.072 MHz

4.608 MHz

6 MHz

96 kHz

1.536 MHz

2.304 MHz

3.072 MHz

4.608 MHz

6.144 MHz

9.216 MHz

12 MHz

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

128

192

250

256

384

500

512

48 kHz

6.144 MHz

9.216 MHz

12 MHz

12.288 MHz

18.432 MHz

24 MHz

24.576 MHz

96 kHz

12.288 MHz

18.432 MHz

24 MHz

24.576 MHz

Table 8-6. Supported SBCLK Frequencies (44.1 kHz based sample rates)

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

125

44.1 kHz

705.6 kHz

1.0584 MHz

1.4112 MHz

2.1168 MHz

2.8224 MHz

4.2336 MHz

5.5125 MHz

88.2 kHz

1.4112 MHz

2.1168 MHz

2.8224 MHz

4.2336 MHz

5.6448 MHz

8.4672 MHz

11.025 MHz

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

128

192

250

256

384

500

512

44.1 kHz

5.6448 MHz

8.4672 MHz

11.025 MHz

11.2896 MHz

16.9344 MHz

22.05 MHz

22.5792 MHz

88.2 kHz

11.2896 MHz

16.9344 MHz

22.05 MHz

22.5792 MHz

If the sample rate is properly configured via the SAMP_RATE[2:0] register bits, no additional configuration is

required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and

SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock

error is detected, the device will enter a low power halt mode after a time set by CLK_HALT_TIMER[2:0] register

bits if DIS_CLK_HALT bit is low. Additionally, the device can automatically power up and down on valid clock

signals if CLK_PWR_UD_EN register bit is set to high. The device sampling rate should not be changed while

this feature is enabled. In this mode the DIS_CLK_HALT bit register should be set low in order for this feature to

work properly.

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TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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