TAS2780 datasheet(85/97 Pages) TI

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11 Power Supply Recommendations

The power sequence between the supply rails can be applied in any order as long as SDZ pin is held low.

Once all supplies are stable the SDZ pin can be set high to initialize the part. After a hardware or software reset

additional commands to the device should be delayed for at least 1 ms to allow the OTP memory to load (see

section Section 10).

When VBAT1S is internally generated (see below Section 11.1) it is recommended that the device enters

Software Shutdown mode before entering Hardware Shutdown mode. This ensures that VBAT1S pin is

discharged using the internal 5 kOhms pull down resistor (not present in Hardware Shutdown mode).

11.1 Power Supply Modes

The TAS2780 can operate with both VBAT1S and PVDD as supplies or with only PVDD or VBAT1S as supply.

The table below shows different power supply modes of operation depending on the customer need.

Table 11-1. Device Configuration and Power Supply Modes

Supply Power Mode

Output

Switching

Mode

Supply

Condition

VBAT1S

Mode

Device

Configurations

Use Case and Device Functionality

PWR_MODE0

High Power on

PVDD

PVDD>VBAT1S

External

VBAT1S_MODE=0

CDS_MODE[1:0]=10

PVDD is the only supply used to deliver

output power.

PWR_MODE1

Y Bridge - High

Power on

VBAT1S

PVDD

External

VBAT1S_MODE=0

CDS_MODE[1:0]=00

VBAT1S is used to deliver output

power based on level and headroom

configured. When audio signal crosses

a programmed threshold Class-D output

is switched over PVDD.

PWR_MODE2

Y Bridge - Low

Power on

VBAT1S

PVDD

Internal

VBAT1S_MODE=1

CDS_MODE[1:0]=11

PVDD is the only supply. VBAT1S is

delivered by an internal LDO and used

to supply at signals close to idle channel

levels. When audio signal levels crosses

-100dBFS (default), Class-D output

switches to PVDD.

PWR_MODE3

VBAT1S

External

VBAT1S_MODE=0

CDS_MODE[1:0]=01

The device can be forced to work out

of a low power rail mode of operation.

For example this can be used for a low

power ultrasonic chirp when audio is not

played.

When VBAT1S is external (PWR_MODE0, PWR_MODE1), if PVDD falls below (VBAT1S+2.5V) level, the Y-

bridge will stop switching between supplies and will remain on the PVDD supply.

In PWR_MODE2 customer needs to ensure that PVDD supply level is at least 2.5 V above the VBAT1S voltage

generated internally in order to take advantage of Y bridge mode of operation. To enable voltage protection the

under-voltage threshold of PVDD supply should be set above 7.3 V by using register bits PVDD_UVLO[5:0].

This will ensure that, with an internally generated VBAT1S of 4.8 V, PVDD supply is at least 2.5 V higher than

VBAT1S.

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TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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