TAS2780 datasheet(22/97 Pages) TI

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decoupling capacitor should still be populated as recommended in Table 9-1. In this case, VBAT1S_MODE

bit should be set to high before transitioning from software shutdown. More details about VBAT1S supply modes

of operation can be found in Section 11.1.

8.4.2.5 Low Voltage Signaling (LVS)

The TAS2780 monitors the absolute value of the audio stream.

When the input is initially above the programmed fixed threshold set by LVS_FTH[4:0] register bits, the Class-D

is supplied by the PVDD rail. When the signal level drops below this threshold for longer than the hysteresis time

defined by LVS_HYS[3:0] bits the Class-D supply will switch to VBAT1S (see Figure 8-4).

All values of LVS_HYS[3:0] bit settings will ensure the remaining samples will be output before BYP_EN pin is

asserted (high). When multiple devices have BYP_EN pin connected together, any of the devices requiring a

supply voltage higher than the threshold will pull the open drain output low.

When the signal level crosses above the programmed fixed threshold set by LVS_FTH[4:0] bits the Class-D

supply will switch to PVDD.

The open-drain BYP_EN pin will be de-asserted (actively pulling the output low) after a delay programmed by

the LVS_DLY[1:0] register bits . The Y Bridge will switch from the VBAT1S suppl to the PVDD supply after a

delay programmed by the CDS_DLY[1:0] register bits.

The fixed LVS threshold is set based on the output signal level and is measured in dBFS.

By default, the LVS threshold is configured to be a value relative to the VBAT1S voltage. The LVS_TMODE bit is

set to high and the LVS_RTH[3:0] register bits are set to 3'b010 (0.7 V from VBAT1S).

Figure 8-4. Low Voltage Signaling

The LVS fixed thresholds, when CDS_MODE[1:0]=11 (PWR_MODE2 from Section 11.1), can be set using

thresholds should be set with register bits LVS_FTH[4:0].

BOP, Limiter, Thermal Foldback and Thermal Gradient gain attenuations should not be taken into account for

calculating LVS threshold.

8.4.2.6 Y-Bridge

The TAS2780 Class-D output uses a Y-Bridge configuration to improve efficiency during playback. The LVS

(Section 8.4.2.5) is internally used to select between the PVDD and VBAT1S supplies. This feature is enabled by

setting CDS_MODE[1:0] bits to 2'b00 when both PVDD and VBAT1S are supplied externally to the device. In this

case the VBAT1S rail must be capable of delivering power (up to 1 W).

TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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TAS2780 Datasheet(PDF) 22 Page - Texas Instruments