TAS2780 datasheet(27/97 Pages) TI

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the SDOUT pin (TDM bus). If the ICC pin is disabled or used for GPIO functionality, the ICGA (Section 8.4.2.10)

will occur on the TDM bus instead of the ICC pin. Register bits ICC_MODE[2:0] are used to set the ICC pin

functionality.

8.4.2.11 Class-D Settings

8.4.2.11.1 Synchronization

The TAS2780 Class-D amplifier supports spread spectrum PWM modulation, which can be enabled by setting

the AMP_SS register bit high. This can help reduce EMI in the system.

By default the Class-D amplifier switching frequency is based on the device trimmed internal oscillator. To

synchronize switching to the audio sample rate, set the CLASSD_SYNC register bit high. When the Class-D is

synchronized to the audio sample rate, the RAMP_RATE register bit must be set depending on the audio sample

rate of either 44.1 kHz or 48 kHz based frequency.

For 44.1, 88.2 and 176.4 kHz, set RAMP_RATE bit high and for 48, 96 and 192 kHz, set this bit low. This

ensures that the internal ramp generator has the appropriate slope.

8.4.2.11.2 Output Slew Rate Control

The output slew rate can be programmed using register bits EDGE_CTRL[1:0] form page 0x01, register 0x4C.

By default, if PVDD supply is below 20 V the output slew rate will be fast. If PVDD goes above 20 V the slew rate

will be automatically change to slow.

Optionally, to improve EMI performance, is to set the slew rate to slow for the entire range of PVDD supply by

setting the bits EDGE_CTRL[1:0] to 2'b11.

8.4.3 SAR ADC

A SAR ADC monitors PVDD voltage, VBAT1S voltage and die temperature. The results of these conversions are

available via register readback (PVDD_CNV[11:0], VBAT1S_CNV[11:0] and TMP_CNV[7:0] register bits). PVDD

and VBAT1S voltage conversions are also used by the limiter and brown out prevention blocks.

By default, VBAT1S conversion is enabled along with PVDD and temperature in both cases, when BOP source

is VBAT1S (BOP_SRC=0) or BOP source is PVDD (BOP_SRC=1). To disable VBAT1S conversion set the bit

The ADC runs at a fixed 192 kHz sample rate with a conversion time of 5.2 µs.

Sampling rate for temperature is 10K samples/sec.

PVDD and VBAT1S voltages and the die temperature are calculated using equations from Registers 0x52 to

0x56 of Page 0x00.

The register bits content should always be read from MSB to LSB.

8.4.4 Current and Voltage (IV) Sense

The TAS2780 provides speaker voltage and current sense measurements for real time monitoring of

loudspeaker behavior. The VSNS_P and VSNS_N pins should be connected after any ferrite bead filter or

directly to the OUT_P and OUT_N connections if no EMI filter is used. The V-Sense connections eliminate

voltage drop error due to packaging, PCB interconnect or ferrite bead filter resistance. The V-sense connections

are also used for Post Filter Feed-Back (Section 8.4.5) to correct for any voltage drop induced gain error or

non-linearity due to the ferrite bead. It should be noted that any interconnect resistance after the VSNS terminals

will not be corrected for, so it is advised to connect the VSNS pins as close to the load as possible.

The voltage and current sense ADCs have a DC blocking filter. This filter cut-off frequency can be adjusted, or

the filter can be bypassed using the HPF_FREQ_REC[2:0] register bits.

I-Sense and V-Sense blocks can be powered down by asserting the ISNS_PD and VSNS_PD register bits

respectively. When powered down, the device will return null samples for the powered down block.

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TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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