TAS2780 datasheet(26/97 Pages) TI

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A hold condition (infinite or not) for a higher BOP level will not be reached if the supply ramps up faster than the

lower levels release. Specifically, whether the infinite hold for a level is reached or not, it depends on the release

rates of the lower levels, so even if infinite hold is set, it might not be reached.

8.4.2.9 Low Battery Tracking Limiter (LBTL)

The VBAT1S limiter attenuates the channel gain at lower VBAT1S voltages (< 3.2 V) to reduce the maximum

power delivery and prevent thermal shutdown.

Using the SAR measurement on VBAT1S the limiter calculates its gain based on the equation below.

LBTL_GAIN (dBV) = 21dBV + VBLIM_GAIN (dBV)

(3)

If the programmed signal gain (amplifier level and DVC) meets the following condition:

AAMP + ADVC < LBTL_GAIN,

(4)

the LBTL mechanism will not be activated.

The VBLIM_GAIN from equation (3) is dependent on VBAT1S level (see the table below).

Table 8-3. VBLIM_GAIN vs VBAT1S

VBAT1S [V]

VBLIM_GAIN [dBV]

3.2

3.1

-0.5

-0.75

2.9

-1.2

2.8

-1.56

2.7

-2

The overall gain in the signal chain will be the minimum of gains defined by SPL, BOP and LBTL.

8.4.2.10 Inter Chip Gain Alignment (ICGA)

The TAS2780 supports alignment of STL and brownout BOP dynamics across devices using the dedicated ICC

feature (Section 8.4.2.10.1) or across the TDM output bus (SDOUT). This ensures consistent gain between

channels during limiting or brownout events since these dynamics are dependent on audio content, which can

vary across channels. Each device can be configured to align to a specified number of other devices, which

allows creation of groupings of devices that align only to each other.

STL and BOP activity is optionally transmitted by each device on SDOUT pin or ICC pin in a 24-bit time slot.

When both limiter and brownout are enabled, the data is comprised of an 11-bit word for limiter and a 13-bit

word for brownout data. If only the limiter is enabled, the data will be 12-bit word for limiter data. Gain reduction

should be transmitted in adjacent time slots for all devices that are to be aligned beginning with the first slot that

is specified by the ICGA_SLOT[5:0] register bits. The order of the devices is not important as long as they are

adjacent. The time slot for limiter gain reduction is configured by the GAIN_SLOT[5:0] register bits and enabled

by the GAIN_TX register bit being set high. The ICGA_SEN[7:0] register bits specify which time slots should be

listened to for gain alignment. This allows any number of devices between two and eight to be grouped together.

At least two of these devices should be enabled for alignment to take place.

To enable the inter-chip limiter alignment the ICLA_EN register bit should be set to high. To enable the inter chip

BOP alignment the ICBA_EN register bit should be set to high. All devices should be configured with identical

limiter and brownout prevention settings.

8.4.2.10.1 Inter-Chip Communication (ICC) Pin

The TAS2780 has a dedicated ICC bus pin that enables gain alignment (ICGA) without consuming slots on the

TDM bus. The ICC pin is connected to all TAS2780 devices in the system and slots are configured using register

bits GAIN_SLOT[5:0]. This bus uses the TDM (Section 8.4.1) BCLK and FSYNC inputs and requires all devices

to be configured using the same sampling clock. The ICC pin supports separate bus keeper configuration from

TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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