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TAS2780 Datasheet(PDF) 65 Page - Texas Instruments |
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TAS2780 Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 97 page  Bit Field Type Reset Description 5-3 CLK_HALT_TIMER[2:0] RW 3h Clock halt timer values 0h = 820 μs 1h = 3.27 ms 2h = 26.21 ms 3h =52.42 ms 4h = 104.85 ms 5h = 209.71 ms 6h = 419.43 ms 7h = 838.86 ms 2 INT_LTCH_CLR RW 0h Clear interrupt latch registers 0h = Don't clear 1h = Clear (self clearing bit) 1-0 IRQZ_PIN_CFG[1:0] RW 1h IRQZ interrupt configuration. IRQZ will assert 0h = On any unmasked live interrupts 1h = On any unmasked latched interrupts 2h = For 2 - 4 ms one time on any unmasked live interrupt event 3h = For 2 - 4 ms every 4 ms on any unmasked latched interrupts 8.9.84 MISC_CFG3 (page=0x00 address=0x5D) [reset=80h] Bit Field Type Reset Description 7 IRQZ_POL RW 1h IRQZ pin polarity for interrupt 0h = Active high (IRQ) 1h = Active low (IRQZ) 6-4 Reserved RW 0h Reserved 3-2 YB_BOP_CTRL[1:0] RW 0h This register selects on which BOP level, Y-bridge and BYP_EN pad need to shift to PVDD when BOP_SRC=0 0h = shift to PVDD when BOP LVL0 is detected 1h = shift to PVDD when BOP LVL1 or LVL0 is detected 2h = shift to PVDD when BOP LVL2 or LVL1 or LVL0 is detected 3h = shift to PVDD when BOP LVL3 or LVL2 or LVL1 or LVL0 is detected 1-0 Reserved RW 0h Reserved 8.9.85 CLOCK_CFG (page=0x00 address=0x60) [reset=0Dh] Bit Field Type Reset Description 7-6 Reserved R 0h Reserved 5-2 SAMP_RATIO[3:0] RW 3h SBCLK to FS ratio when AUTO_RATE = 1 (disabled) 00h = 16 01h = 24 02h = 32 03h = 48 04h = 64 05h = 96 06h = 128 07h = 192 08h = 256 09h = 384 0Ah = 512 0Bh = 125 0Ch = 250 0Dh = 500 0Eh-0Fh = Reserved 1-0 Reserved RW 1h Reserved www.ti.com TAS2780 SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: TAS2780 |
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