TAS2780 datasheet(20/97 Pages) TI

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TX_FILL register bit is used in mono systems where there is only one amplifier on I2S bus. All the slots unused

by the amplifier will be filled with zeros when TX_FILL register bit is set to low.

The SDOUT_HIZ registers from page 0x01 are useful when multiple devices are on the same I2S bus. Each

device does not know the configuration of slots in the other devices on the bus. It is required at the system level

to program the SDOUT_HIZ registers appropriately, in such way that the settings are done correctly and do not

create any contention, internally and externally.

Each sample stream is composed of either one or two 8 bit time slots. Speaker voltage sense and speaker

current sense sample streams are 16 bit precision, so they will always utilize two TX time slots. The PVDD and

VBAT1S voltage streams are 10 bit precision, and can either be transmitted left justified in a 16 bit word (using

two time slots) or can be truncated to 8 bits (the top 8 MSBs) and be transmitted in a single time slot. This is

configured by setting PVDD_SLEN and VBAT1S_SLEN register bits. The die temperature and the gain are both

8 bit precision and are transmitted in a single time slot.

The time slot register for each sample stream defines where the MSB transmission begins. By default

VSNS_SLOT[5:0] register bits are set to 2 (decimal), the upper 8 MSBs will be transmitted in time slot 2 and the

lower 8 LSBs will be transmitted in time slot 3. This sample stream can be individually enabled or disabled by

using VSNS_TX register bit. The ISNS_SLOT[5:0] register bits are set by default to 0 (decimal) and the sample

stream can be enabled or disabled by using ISNS_TX register bit. The enable/disable feature of the streams is

useful to manage limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on

the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. This

will avoid producing unpredictable transmission results in the conflicting bit slots (i.e. the priority is not defined).

The current and voltage values are transmitted at the full 16 bit measured values by default. The

IVMON_LEN[1:0] register bits can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values

across multiple slots. The special 12 bit mode is used when only 24 bit I2S/ TDM data can be processed by the

host processor. The device should be configured with the voltage-sense slot and current-sense slot off by 1 slot

and will consume 3 consecutive 8 bit slots. In this mode the device will transmit the first 12 MSB bits followed by

the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at

the frame boundary.

The time slots for VBAT1S, PVDD and temperature measurements are set using VBAT1S_SLOT[5:0],

PVDD_SLOT[5:0] and TEMP_SLOT[5:0] register bits. To enable each of the sample streams, register bits

VBAT1S_TX, PVDD_TX and TEMP_TX must be set high. The slot length is selected by VBAT1S_SLEN and

PVDD_SLEN register bits.

For TDM final processed audio slot, enable and length settings, use AUDIO_SLOT[5:0], AUDIO_TX and

AUDIO_SLEN register bits.

Information about status of slots can be find in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set

high enables the status transmit.

The slot configuration for the TX limiter gain reduction can be set between 0 (default) and 63 by setting

GAIN_SLOT[5:0] register bits. It is used for ICC (Section 8.4.2.10) and can be either over the TDM bus or ICC

bus. To use this feature, the register bit GAIN_TX needs to be set high.

8.4.2 Playback Signal Path

8.4.2.1 High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The

TAS2780 employs a high-pass filter (HPF) to prevent this from occurring for the PCM playback path. The

HPF_FREQ_PB[2:0] register bits set the corner frequencies of HPF. The filter can be bypassed by setting the

TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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