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TAS2780 Datasheet(PDF) 8 Page - Texas Instruments |
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TAS2780 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 97 page  TA = 25 °C, PVDD = 18 V, VBAT1S = 3.8 V, AVDD = 1.8V, IOVDD =1.8 V, RL = 4Ω + 15µH, fin = 1 kHz, fs = 48 kHz, Gain = 21 dBV, SDZ = 1, NG_EN=0, EN_LLSR=0, PWR_MODE1(2), measured filter free as in Section 7 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCM PLAYBACK CHARACTERISTICS fs > 48 kHz fs Minimum Sample Rates 88.2 kHz Maximum Sample Rate 96 Frequency for Passband Ripple fs = 96 kHz 0.437 fs Passband 3db Frequency fs = 96 kHz 0.459 fs Passband Ripple DC to LPF cutoff frequency -0.5 0.5 dB Stop Band Attenuation ≥ 0.56 fs 60 dB ≥ 1 fs 65 Group Delay (Including Noise Gate) DC to 0.375 fs for 96 kHz, DC blocker disabled 35 1/fs SPEAKER CURRENT SENSE Resolution 16 bits DNR Dynamic Range Un-weighted, relative to 0 dBFS. 70 dB THD+N Total Harmonic Distortion and Noise Pout = 15 W -64 dB Full Scale Input Current Measured at -6 dBFS. Re-scaled at 0 dBFS. 5 A Differential Mode Gain 0.98 1.02 Frequency Response 20 Hz - 20 kHz -0.1 0.1 dB Group Delay 5 1/fs SPEAKER VOLTAGE SENSE Resolution 16 bits DNR Dynamic Range Un-Weighted, Relative 0 dBFS 75 dB THD+N Total Harmonic Distortion and Noise Pout = 15 W -71 dB Full Scale Input Voltage 16 VPK Differential Mode Gain 0.98 1.02 Frequency Response 20 Hz - 20 kHz -0.1 0.1 dB Group Delay 5 1/fs SPEAKER VOLTAGE/CURRENT SENSE RATIO Gain Linearity Pout ≥ 40 mW to 0.1% THD+N, using a 40 Hz -40 dBFS pilot tone, PWR_MODE0 and PWR_MODE1 -1 1 % Gain error over temperature -20°C to 70°C, Pout = 1 W ±0.6 % Phase Error between V and I 300 ns PROTECTION CIRCUITRY Brownout Prevention Latency to First Attack BOP_SRC=1 19 µs Thermal Shutdown Temperature 142 °C Thermal Shutdown Retry OTE_RETRY=1 1.5 s Output Over Current Limit on PVDD Output to Output, Output to GND or Output to PVDD Short 5.5 6.6 A Output Over Current Limit on VBAT1S Output to Output, Output to GND or Output to VBAT1S Short 2 2.6 A VBAT1S Undervoltage Lockout Threshold UVLO is asserted 2 V UVLO is de-asserted 2.16 AVDD Undervoltage Lockout Threshold UVLO is asserted 1.45 V UVLO is de-asserted 1.51 IOVDD Undervoltage Lockout Threshold UVLO is asserted 1.13 V UVLO is de-asserted 1.25 TAS2780 SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022 www.ti.com 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TAS2780 |
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