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CS47L35 Datasheet(PDF) 223 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 223 Page - Cirrus Logic |
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223 / 300 page ![]() DS1085F3 223 CS47L35 4.20 JTAG Interface 4.20 JTAG Interface The JTAG interface provides test and debug access to the CS47L35 DSP core. The interface comprises five pins, as detailed below. • TCK: clock input • TDI: data input • TDO: data output • TMS: mode select input • TRST: test access port reset input (active low) For normal operation (test and debug access disabled), the JTAG interface should be held in reset (i.e., TRST should be at Logic 0). An internal pull-down resistor holds the TRST pin low when not actively driven. External connection to DGND is recommended, if the JTAG interface function is not required. The other JTAG input pins (TCK, TDI, TMS) should also be held at Logic 0 for normal operation. An internal pull-down resistor holds these pins low when not actively driven. If the JTAG interface is enabled (TRST deasserted and TCK active) at the time of any reset, a software reset must be scheduled, with the TCK input stopped or TRST asserted (Logic 0), before using the JTAG interface. It is recommended to always schedule a software reset before starting the JTAG clock or deasserting the JTAG reset. In this event, the JTAG interface should be held in its reset state until the software reset has completed, and the BOOT_ DONE_STSx bits have been set. See Section 4.23 for further details of the CS47L35 software reset. 4.21 Thermal, Short-Circuit, and Timer-Controlled Protection The CS47L35 incorporates thermal protection, short-circuit detection, and timer-controlled speaker disable functions; these are described in the following subsections. 4.21.1 Thermal Shutdown The temperature sensor detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition. The temperature sensor is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.15. A two-stage indication is provided, via the SPK_OVERHEAT_WARN_EINTn and SPK_OVERHEAT_EINTn interrupts. If the upper temperature threshold (SPK_OVERHEAT_EINTn) is exceeded, the Class D speaker outputs are automatically disabled in order to protect the device. When the speaker driver shutdown is complete, a further interrupt, SPK_SHUTDOWN_EINTn, is asserted. 0x06 1.050 V 0x0F 1.275 V 0x1D 2.300 V 0x07 1.075 V 0x15 1.500 V 0x1E 2.400V 0x08 1.100 V 0x16 1.600 V 0x1F 2.500 V 0x09 1.125 V 0x17 1.700 V 0x25 3.100 V 0x0A 1.150 V 0x18 1.800 V 0x26 3.200 V 0x0B 1.175 V 0x19 1.900 V 0x27 3.300 V 0x0C 1.200 V 0x1A 2.000 V 0x28 to 0x3F 3.300 V 0x0D 1.225 V 0x1B 2.100 V Table 4-113. LDO2 Voltage Control (Cont.) LDO2_VSEL[5:0] LDO Output LDO2_VSEL[5:0] LDO Output LDO2_VSEL[5:0] LDO Output |
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