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CS47L35 Datasheet(PDF) 226 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 226 Page - Cirrus Logic |
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226 / 300 page  226 DS1085F3 CS47L35 4.23 Hardware Reset, Software Reset, Wake-Up, and Device ID 4.23 Hardware Reset, Software Reset, Wake-Up, and Device ID The CS47L35 supports hardware- and software-controlled reset functions. The reset functions, and the Sleep/Wake-Up state transitions, provide similar (but not identical) functionality. Each of these is described in the following subsections. The CS47L35 device ID can be read from the Software_Reset (R0) control register, as described in Section 4.23.7. 4.23.1 Hardware Reset The CS47L35 provides a hardware reset function, which is executed whenever the RESET input is asserted (Logic 0). The RESET input is active low and is referenced to the DBVDD1 power domain. A hardware reset causes all of the CS47L35 control registers to be reset to their default states. An internal pull-up resistor is enabled by default on the RESET pin; this can be configured using the RESET_PU bit. A pull-down resistor is also available, as described in Table 4-117. When the pull-up and pull-down resistors are both enabled, the CS47L35 provides a bus keeper function on the RESET pin. The bus keeper function holds the input logic level unchanged whenever the external circuit removes the drive (e.g., if the signal is tristated). If the CS47L35 SLIMbus component is in its operational state, it must be reset prior to scheduling a hardware reset. See Section 4.10 for details of the SLIMbus reset control messages. DBVDD2 P6 AIF2BCLK/GPIO13 Digital I/O Digital input (GPIO), bus-keeper enabled 2 M6 AIF2LRCLK/GPIO15 Digital I/O Digital input (GPIO), bus-keeper enabled 2 K6 AIF2RXDAT/GPIO14 Digital I/O Digital input (GPIO), bus-keeper enabled 2 L5 AIF2TXDAT/GPIO12 Digital I/O Digital input (GPIO), bus-keeper enabled 2 R5 AIF3BCLK/GPIO2 Digital I/O Digital input (GPIO), bus-keeper enabled 2 N5 AIF3LRCLK/GPIO4 Digital I/O Digital input (GPIO), bus-keeper enabled 2 P4 AIF3RXDAT/GPIO3 Digital I/O Digital input (GPIO), bus-keeper enabled 2 M4 AIF3TXDAT/GPIO1 Digital I/O Digital input (GPIO), bus-keeper enabled 2 T6 MCLK2 Digital input Digital input M2 SPKCLK/GPIO6 Digital I/O Digital input (GPIO), bus-keeper enabled 2 N3 SPKDAT/GPIO5 Digital I/O Digital input (GPIO), bus-keeper enabled 2 R7 TCK Digital input Digital input, Pull-down to DGND N7 TDI Digital input Digital input, Pull-down to DGND L7 TDO Digital output Digital output K8 TMS Digital input Digital input, Pull-down to DGND M8 TRST Digital input Digital input, Pull-down to DGND 1.The dual-function INnLN/DMICCLKn and INnRN/DMICDATn pins default to their respective analog input functions after power-on reset is completed. The analog input functions are referenced to the MICVDD power domain. 2.The power-up condition of the GPIO pins depends upon whether the pin is actively driven by another device when the CS47L35 starts up. If the pin is actively driven, the bus keeper maintains this logic level. If the pin is not actively driven, the bus keeper may establish either a Logic 1 or Logic 0 as the default input level. Table 4-117. Reset Pull-Up/Pull-Down Configuration Register Address Bit Label Default Description R6864 (0x1AD0) AOD_Pad_Ctrl 1 RESET_PU 1 RESET Pull-up enable 0 = Disabled 1 = Enabled Note: If RESET_PD and RESET_PU are both set, a bus keeper function is enabled on the RESET pin. 0 RESET_PD 0 RESET Pull-down enable 0 = Disabled 1 = Enabled Note: If RESET_PD and RESET_PU are both set, a bus keeper function is enabled on the RESET pin. Table 4-116. CS47L35 Digital I/O Status in Reset (Cont.) Power Domain Pin No Name Type Reset Status |
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