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CS47L35 Datasheet(PDF) 242 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 242 Page - Cirrus Logic |
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242 / 300 page  242 DS1085F3 CS47L35 5.4 Digital Audio Interface Clocking Configurations Fig. 5-17 shows AIF Slave Mode operation, using MCLK as the clock reference. For correct operation, the MCLK input must be fully synchronized to the audio interface. Figure 5-17. AIF Slave Mode, Using MCLK as Reference Fig. 5-18 shows AIF Slave Mode operation, using MCLK as the clock reference. For correct operation, the MCLK input must be fully synchronized to the audio interface. In this example, the FLL is used to generate the system clock, with MCLK as the reference. Figure 5-18. AIF Slave Mode, Using MCLK and FLL as Reference Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK SYSCLK_SRC Synchronous Clock Generator AIFn (Slave Mode) AIFnBCLK FLL1 SLIMCLK CS47L35 AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 Processor Synchronous Clock Generator SYSCLK SYSCLK_SRC AIFn (Slave Mode) AIFnBCLK SLIMCLK MCLK1 MCLK2 AIFnLRCLK AIFnBCLK SLIMCLK CS47L35 |
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