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CS47L35 Datasheet(PDF) 245 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 245 Page - Cirrus Logic

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DS1085F3
245
CS47L35
6 Register Map
R105
(69h)
Spare_Sequence_
Select_14
00
000
00
WSEQ_TRG14_INDEX [8:0]
01FFh
R106
(6Ah)
Spare_Sequence_
Select_15
00
000
00
WSEQ_TRG15_INDEX [8:0]
01FFh
R107
(6Bh)
Spare_Sequence_
Select_16
00
000
00
WSEQ_TRG16_INDEX [8:0]
01FFh
R110
(6Eh)
Trigger_Sequence_
Select_32
00
000
00
WSEQ_DRC1_SIG_DET_RISE_INDEX [8:0]
01FFh
R111
(6Fh)
Trigger_Sequence_
Select_33
00
000
00
WSEQ_DRC1_SIG_DET_FALL_INDEX [8:0]
01FFh
R120
(78h)
Eventlog_Sequence_
Select_1
0
0
0
0
0
0
0
WSEQ_EVENTLOG1_INDEX [8:0]
01FFh
R121
(79h)
Eventlog_Sequence_
Select_2
0
0
0
0
0
0
0
WSEQ_EVENTLOG2_INDEX [8:0]
01FFh
R122
(7Ah)
Eventlog_Sequence_
Select_3
0
0
0
0
0
0
0
WSEQ_EVENTLOG3_INDEX [8:0]
01FFh
R123
(7Bh)
Eventlog_Sequence_
Select_4
0
0
0
0
0
0
0
WSEQ_EVENTLOG4_INDEX [8:0]
01FFh
R144
(90h)
Haptics_Control_1
0
HAP_RATE [3:0]
0
0
0
0
0
0
ONESHOT
_TRIG
HAP_CTRL [1:0]
HAP_ACT
0
0000h
R145
(91h)
Haptics_Control_2
0
LRA_FREQ [14:0]
7FFFh
R146
(92h)
Haptics_phase_1_
intensity
00
000
000
PHASE1_INTENSITY [7:0]
0000h
R147
(93h)
Haptics_phase_1_
duration
00
000
00
PHASE1_DURATION [8:0]
0000h
R148
(94h)
Haptics_phase_2_
intensity
00
000
000
PHASE2_INTENSITY [7:0]
0000h
R149
(95h)
Haptics_phase_2_
duration
00
000
PHASE2_DURATION [10:0]
0000h
R150
(96h)
Haptics_phase_3_
intensity
00
000
000
PHASE3_INTENSITY [7:0]
0000h
R151
(97h)
Haptics_phase_3_
duration
00
000
00
PHASE3_DURATION [8:0]
0000h
R152
(98h)
Haptics_Status
00
000
000
00
000
00
ONESHOT
_STS
0000h
R160
(A0h)
Comfort_Noise_
Generator
0
NOISE_GEN_RATE [3:0]
0
0
0
0
0
NOISE_
GEN_ENA
NOISE_GEN_GAIN [4:0]
0000h
R256
(100h)
Clock_32k_1
00
000
000
0
CLK_32K_
ENA
0
0
0
0
CLK_32K_SRC [1:0]
0002h
R257
(101h)
System_Clock_1
SYSCLK_
FRAC
0
0
0
0
SYSCLK_FREQ [2:0]
0
SYSCLK_
ENA
0
0
SYSCLK_SRC [3:0]
0404h
R258
(102h)
Sample_rate_1
00
000
000
00
0
SAMPLE_RATE_1 [4:0]
0011h
R259
(103h)
Sample_rate_2
00
000
000
00
0
SAMPLE_RATE_2 [4:0]
0011h
R260
(104h)
Sample_rate_3
00
000
000
00
0
SAMPLE_RATE_3 [4:0]
0011h
R266
(10Ah)
Sample_rate_1_status
00
000
000
00
0
SAMPLE_RATE_1_STS [4:0]
0000h
R267
(10Bh)
Sample_rate_2_status
00
000
000
00
0
SAMPLE_RATE_2_STS [4:0]
0000h
R268
(10Ch)
Sample_rate_3_status
00
000
000
00
0
SAMPLE_RATE_3_STS [4:0]
0000h
R288
(120h)
DSP_Clock_1
0
0
0
0
0
DSP_CLK_FREQ_RANGE [2:0]
0
DSP_
CLK_ENA
0
0
DSP_CLK_SRC [3:0]
0305h
R329
(149h)
Output_system_clock
OPCLK_
ENA
0
000
000
OPCLK_DIV [4:0]
OPCLK_SEL [2:0]
0000h
R334
(14Eh)
Clock_Gen_Pad_Ctrl
00
000
00
MCLK2_
PD
MCLK1_
PD
0
000
000
0000h
R338
(152h)
Rate_Estimator_1
00
000
000
00
0
TRIG_ON_
STARTUP
LRCLK_SRC [2:0]
RATE_
EST_ENA
0000h
R339
(153h)
Rate_Estimator_2
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE_DETECT_A [4:0]
0000h
R340
(154h)
Rate_Estimator_3
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE_DETECT_B [4:0]
0000h
R341
(155h)
Rate_Estimator_4
00
000
000
00
0
SAMPLE_RATE_DETECT_C [4:0]
0000h
R342
(156h)
Rate_Estimator_5
00
000
000
00
0
SAMPLE_RATE_DETECT_D [4:0]
0000h
R369
(171h)
FLL1_Control_1
00
000
000
00
000
0
FLL1_
FREERUN
FLL1_ENA
0002h
R370
(172h)
FLL1_Control_2
FLL1_
CTRL_
UPD
0
0
0
0
0
FLL1_N [9:0]
0008h
R371
(173h)
FLL1_Control_3
FLL1_THETA [15:0]
0018h
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default



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