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CS47L35 Datasheet(PDF) 247 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 247 Page - Cirrus Logic

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DS1085F3
247
CS47L35
6 Register Map
R769
(301h)
Input_Enables_Status
00
000
000
00
00
IN2L_
ENA_STS
IN2R_
ENA_STS
IN1L_
ENA_STS
IN1R_
ENA_STS
0000h
R776
(308h)
Input_Rate
0
IN_RATE [3:0]
000
00
000
000
0000h
R777
(309h)
Input_Volume_Ramp
0
0
0
0
0
0
0
0
0
IN_VD_RAMP [2:0]
0
IN_VI_RAMP [2:0]
0022h
R780
(30Ch)
HPF_Control
00
000
000
00
000
IN_HPF_CUT [2:0]
0002h
R784
(310h)
IN1L_Control
IN1L_HPF
0
0
IN1_DMIC_SUP [1:0]
IN1_
MODE
0
0
IN1L_PGA_VOL [6:0]
0
0080h
R785
(311h)
ADC_Digital_Volume_1L
0
IN1L_SRC [1:0]
0
0
0
IN_VU
IN1L_
MUTE
IN1L_VOL [7:0]
0180h
R786
(312h)
DMIC1L_Control
0
0
0
0
0
IN1_OSR [2:0]
0
0
IN1L_DMIC_DLY [5:0]
0500h
R788
(314h)
IN1R_Control
IN1R_HPF
0
0
0
0
0
0
0
IN1R_PGA_VOL [6:0]
0
0080h
R789
(315h)
ADC_Digital_Volume_1R
0
IN1R_SRC [1:0]
0
0
0
IN_VU
IN1R_
MUTE
IN1R_VOL [7:0]
0180h
R790
(316h)
DMIC1R_Control
00
000
000
00
IN1R_DMIC_DLY [5:0]
0000h
R792
(318h)
IN2L_Control
IN2L_HPF
0
0
IN2_DMIC_SUP [1:0]
IN2_
MODE
0
0
IN2L_PGA_VOL [6:0]
0
0080h
R793
(319h)
ADC_Digital_Volume_2L
0
IN2L_SRC [1:0]
0
0
0
IN_VU
IN2L_
MUTE
IN2L_VOL [7:0]
0180h
R794
(31Ah)
DMIC2L_Control
0
0
0
0
0
IN2_OSR [2:0]
0
0
IN2L_DMIC_DLY [5:0]
0500h
R796
(31Ch)
IN2R_Control
IN2R_HPF
0
0
0
0
0
0
0
IN2R_PGA_VOL [6:0]
0
0080h
R797
(31Dh)
ADC_Digital_Volume_2R
0
IN2R_SRC [1:0]
0
0
0
IN_VU
IN2R_
MUTE
IN2R_VOL [7:0]
0180h
R798
(31Eh)
DMIC2R_Control
00
000
000
00
IN2R_DMIC_DLY [5:0]
0000h
R840
(348h)
Dig_Mic_Pad_Ctrl
00
000
000
00
000
0
DMICDAT2
_PD
DMICDAT1
_PD
0000h
R1024
(400h)
Output_Enables_1
EP_SEL
0
0
0
0
0
OUT5L_
ENA
OUT5R_
ENA
SPKOUTL
_ENA
0
000
0
HP1L_
ENA
HP1R_
ENA
0000h
R1025
(401h)
Output_Status_1
00
000
0
OUT5L_
ENA_STS
OUT5R_
ENA_STS
OUT4L_
ENA_STS
0
000
000
0000h
R1030
(406h)
Raw_Output_Status_1
00
000
000
00
000
0
OUT1L_
ENA_STS
OUT1R_
ENA_STS
0000h
R1032
(408h)
Output_Rate_1
0
OUT_RATE [3:0]
000
00
000
000
0000h
R1033
(409h)
Output_Volume_Ramp
00
000
000
0
OUT_VD_RAMP [2:0]
0
OUT_VI_RAMP [2:0]
0022h
R1040
(410h)
Output_Path_Config_1L
00
0
OUT1_
MONO
0
000
10
000
000
0080h
R1041
(411h)
DAC_Digital_Volume_1L
00
000
0
OUT_VU OUT1L_
MUTE
OUT1L_VOL [7:0]
0180h
R1043
(413h)
Noise_Gate_Select_1L
00
00
OUT1L_NGATE_SRC [11:0]
0001h
R1045
(415h)
DAC_Digital_Volume_1R
00
000
0
OUT_VU OUT1R_
MUTE
OUT1R_VOL [7:0]
0180h
R1047
(417h)
Noise_Gate_Select_1R
00
00
OUT1R_NGATE_SRC [11:0]
0002h
R1065
(429h)
DAC_Digital_Volume_4L
00
000
0
OUT_VU OUT4L_
MUTE
OUT4L_VOL [7:0]
0180h
R1067
(42Bh)
Noise_Gate_Select_4L
00
00
OUT4L_NGATE_SRC [11:0]
0040h
R1072
(430h)
Output_Path_Config_5L
00
OUT5_
OSR
00
000
00
000
000
0000h
R1073
(431h)
DAC_Digital_Volume_5L
00
000
0
OUT_VU OUT5L_
MUTE
OUT5L_VOL [7:0]
0180h
R1075
(433h)
Noise_Gate_Select_5L
00
00
OUT5L_NGATE_SRC [11:0]
0100h
R1077
(435h)
DAC_Digital_Volume_5R
00
000
0
OUT_VU OUT5R_
MUTE
OUT5R_VOL [7:0]
0180h
R1079
(437h)
Noise_Gate_Select_5R
00
00
OUT5R_NGATE_SRC [11:0]
0200h
R1104
(450h)
DAC_AEC_Control_1
0
0
0
0
0
0
0
0
0
0
AEC1_LOOPBACK_SRC [3:0]
AEC1_
ENA_STS
AEC1_
LOOPBAC
K_ENA
0000h
R1105
(451h)
DAC_AEC_Control_2
0
0
0
0
0
0
0
0
0
0
AEC2_LOOPBACK_SRC [3:0]
AEC2_
ENA_STS
AEC2_
LOOPBAC
K_ENA
0000h
R1112
(458h)
Noise_Gate_Control
00
000
000
00
NGATE_HOLD [1:0]
NGATE_THR [2:0]
NGATE_
ENA
0000h
R1168
(490h)
PDM_SPK1_CTRL_1
0
0
SPK1R_
MUTE
SPK1L_
MUTE
0
0
0
SPK1_
MUTE_
ENDIAN
SPK1_MUTE_SEQ [7:0]
0069h
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default



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