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CS47L35 Datasheet(PDF) 262 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 262 Page - Cirrus Logic

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262
DS1085F3
CS47L35
6 Register Map
R3720
(E88h)
DRC2_ctrl1
DRC2_SIG_DET_RMS [4:0]
DRC2_SIG_DET_PK
[1:0]
DRC2_
NG_ENA
DRC2_
SIG_DET_
MODE
DRC2_
SIG_DET
DRC2_
KNEE2_
OP_ENA
DRC2_QR DRC2_
ANTICLIP
0DRC2L_
ENA
DRC2R_
ENA
0018h
R3721
(E89h)
DRC2_ctrl2
0
0
0
DRC2_ATK [3:0]
DRC2_DCY [3:0]
DRC2_MINGAIN [2:0]
DRC2_MAXGAIN [1:0]
0933h
R3722
(E8Ah)
DRC2_ctrl3
DRC2_NG_MINGAIN [3:0]
DRC2_NG_EXP [1:0] DRC2_QR_THR [1:0] DRC2_QR_DCY [1:0]
DRC2_HI_COMP [2:0]
DRC2_LO_COMP [2:0]
0018h
R3723
(E8Bh)
DRC2_ctrl4
0
0
0
0
0
DRC2_KNEE_IP [5:0]
DRC2_KNEE_OP [4:0]
0000h
R3724
(E8Ch)
DRC2_ctrl5
0
0
0
0
0
0
DRC2_KNEE2_IP [4:0]
DRC2_KNEE2_OP [4:0]
0000h
R3776
(EC0h)
HPLPF1_1
00
000
000
00
000
0
LHPF1_
MODE
LHPF1_
ENA
0000h
R3777
(EC1h)
HPLPF1_2
LHPF1_COEFF [15:0]
0000h
R3780
(EC4h)
HPLPF2_1
00
000
000
00
000
0
LHPF2_
MODE
LHPF2_
ENA
0000h
R3781
(EC5h)
HPLPF2_2
LHPF2_COEFF [15:0]
0000h
R3784
(EC8h)
HPLPF3_1
00
000
000
00
000
0
LHPF3_
MODE
LHPF3_
ENA
0000h
R3785
(EC9h)
HPLPF3_2
LHPF3_COEFF [15:0]
0000h
R3788
(ECCh)
HPLPF4_1
00
000
000
00
000
0
LHPF4_
MODE
LHPF4_
ENA
0000h
R3789
(ECDh)
HPLPF4_2
LHPF4_COEFF [15:0]
0000h
R3824
(EF0h)
ISRC1_CTRL_1
0
ISRC1_FSH [3:0]
000
00
000
000
0000h
R3825
(EF1h)
ISRC1_CTRL_2
0
ISRC1_FSL [3:0]
000
00
000
001
0001h
R3826
(EF2h)
ISRC1_CTRL_3
ISRC1_
INT1_ENA
ISRC1_
INT2_ENA
ISRC1_
INT3_ENA
ISRC1_
INT4_ENA
00
ISRC1_
DEC1_
ENA
ISRC1_
DEC2_
ENA
ISRC1_
DEC3_
ENA
ISRC1_
DEC4_
ENA
000
000
0000h
R3827
(EF3h)
ISRC2_CTRL_1
0
ISRC2_FSH [3:0]
000
00
000
000
0000h
R3828
(EF4h)
ISRC2_CTRL_2
0
ISRC2_FSL [3:0]
000
00
000
001
0001h
R3829
(EF5h)
ISRC2_CTRL_3
ISRC2_
INT1_ENA
ISRC2_
INT2_ENA
ISRC2_
INT3_ENA
ISRC2_
INT4_ENA
00
ISRC2_
DEC1_
ENA
ISRC2_
DEC2_
ENA
ISRC2_
DEC3_
ENA
ISRC2_
DEC4_
ENA
000
000
0000h
R4608
(1200h)
Clock_enable_
overrides_1
00
000
000
00
000
0
FLL1_
ENA1
DSP_
CLK_
ENA1
0000h
R4610
(1202h)
Clock_enable_
overrides_2
00
000
000
00
000
0
FLL1_
ENA2
DSP_
CLK_
ENA2
0000h
R4612
(1204h)
Clock_enable_
overrides_3
00
000
000
00
000
0
FLL1_
ENA3
DSP_
CLK_
ENA3
0000h
R4614
(1206h)
Clock_enable_
overrides_4
00
000
000
00
000
0
FLL1_
ENA4
DSP_
CLK_
ENA4
0000h
R4616
(1208h)
Clock_enable_
overrides_5
00
000
000
00
000
0
FLL1_
ENA5
DSP_
CLK_
ENA5
0000h
R4618
(120Ah)
Clock_enable_
overrides_6
00
000
000
00
000
0
FLL1_
ENA6
DSP_
CLK_
ENA6
0000h
R4620
(120Ch)
Clock_enable_
overrides_7
00
000
000
00
000
0
FLL1_
ENA7
DSP_
CLK_
ENA7
0000h
R4622
(120Eh)
Clock_enable_
overrides_8
00
000
000
00
000
0
FLL1_
ENA8
DSP_
CLK_
ENA8
0000h
R4624
(1210h)
Clock_enable_
overrides_9
00
000
000
00
000
0
FLL1_
ENA9
DSP_
CLK_
ENA9
0000h
R4626
(1212h)
Clock_enable_
overrides_10
00
000
000
00
000
0
FLL1_
ENA10
DSP_
CLK_
ENA10
0000h
R4628
(1214h)
Clock_enable_
overrides_11
00
000
000
00
000
0
FLL1_
ENA11
DSP_
CLK_
ENA11
0000h
R4630
(1216h)
Clock_enable_
overrides_12
00
000
000
00
000
0
FLL1_
ENA12
DSP_
CLK_
ENA12
0000h
R4632
(1218h)
Clock_enable_
overrides_13
00
000
000
00
000
0
FLL1_
ENA13
DSP_
CLK_
ENA13
0000h
R4634
(121Ah)
Clock_enable_
overrides_14
00
000
000
00
000
0
FLL1_
ENA14
DSP_
CLK_
ENA14
0000h
R4636
(121Ch)
Clock_enable_
overrides_15
00
000
000
00
000
0
FLL1_
ENA15
DSP_
CLK_
ENA15
0000h
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default



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