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CS47L35 Datasheet(PDF) 265 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 265 Page - Cirrus Logic |
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265 / 300 page  DS1085F3 265 CS47L35 6 Register Map R6218 (184Ah) IRQ1_Mask_11 IM_DSP_ IRQ16_ EINT1 IM_DSP_ IRQ15_ EINT1 IM_DSP_ IRQ14_ EINT1 IM_DSP_ IRQ13_ EINT1 IM_DSP_ IRQ12_ EINT1 IM_DSP_ IRQ11_ EINT1 IM_DSP_ IRQ10_ EINT1 IM_DSP_ IRQ9_ EINT1 IM_DSP_ IRQ8_ EINT1 IM_DSP_ IRQ7_ EINT1 IM_DSP_ IRQ6_ EINT1 IM_DSP_ IRQ5_ EINT1 IM_DSP_ IRQ4_ EINT1 IM_DSP_ IRQ3_ EINT1 IM_DSP_ IRQ2_ EINT1 IM_DSP_ IRQ1_ EINT1 FFFFh R6219 (184Bh) IRQ1_Mask_12 00 000 000 0 IM_ SPKOUTL _SC_ EINT1 00 IM_HP2R_ SC_EINT1 IM_HP2L_ SC_EINT1 IM_HP1R_ SC_EINT1 IM_HP1L_ SC_EINT1 004Fh R6220 (184Ch) IRQ1_Mask_13 00 000 000 0 IM_ SPKOUTL _ENABLE_ DONE_ EINT1 000 0 IM_HP1R_ ENABLE_ DONE_ EINT1 IM_HP1L_ ENABLE_ DONE_ EINT1 0043h R6221 (184Dh) IRQ1_Mask_14 00 000 000 0 IM_ SPKOUTL _ DISABLE_ DONE_ EINT1 000 0 IM_HP1R_ DISABLE_ DONE_ EINT1 IM_HP1L_ DISABLE_ DONE_ EINT1 0043h R6222 (184Eh) IRQ1_Mask_15 00 000 000 00 000 IM_SPK_ OVERHEA T_WARN_ EINT1 IM_SPK_ OVERHEA T_EINT1 IM_SPK_ SHUTDO WN_EINT1 0007h R6224 (1850h) IRQ1_Mask_17 IM_ GPIO16_ EINT1 IM_ GPIO15_ EINT1 IM_ GPIO14_ EINT1 IM_ GPIO13_ EINT1 IM_ GPIO12_ EINT1 IM_ GPIO11_ EINT1 IM_ GPIO10_ EINT1 IM_ GPIO9_ EINT1 IM_ GPIO8_ EINT1 IM_ GPIO7_ EINT1 IM_ GPIO6_ EINT1 IM_ GPIO5_ EINT1 IM_ GPIO4_ EINT1 IM_ GPIO3_ EINT1 IM_ GPIO2_ EINT1 IM_ GPIO1_ EINT1 FFFFh R6228 (1854h) IRQ1_Mask_21 00 000 000 00 00 IM_ TIMER4_ EINT1 IM_ TIMER3_ EINT1 IM_ TIMER2_ EINT1 IM_ TIMER1_ EINT1 000Fh R6229 (1855h) IRQ1_Mask_22 00 000 000 00 00 IM_ EVENT4_ NOT_ EMPTY_ EINT1 IM_ EVENT3_ NOT_ EMPTY_ EINT1 IM_ EVENT2_ NOT_ EMPTY_ EINT1 IM_ EVENT1_ NOT_ EMPTY_ EINT1 000Fh R6230 (1856h) IRQ1_Mask_23 00 000 000 00 00 IM_ EVENT4_ FULL_ EINT1 IM_ EVENT3_ FULL_ EINT1 IM_ EVENT2_ FULL_ EINT1 IM_ EVENT1_ FULL_ EINT1 000Fh R6231 (1857h) IRQ1_Mask_24 00 000 000 00 00 IM_ EVENT4_ WMARK_ EINT1 IM_ EVENT3_ WMARK_ EINT1 IM_ EVENT2_ WMARK_ EINT1 IM_ EVENT1_ WMARK_ EINT1 000Fh R6232 (1858h) IRQ1_Mask_25 00 000 000 00 000 IM_DSP3_ DMA_ EINT1 IM_DSP2_ DMA_ EINT1 IM_DSP1_ DMA_ EINT1 0007h R6234 (185Ah) IRQ1_Mask_27 00 000 000 00 000 IM_DSP3_ START1_ EINT1 IM_DSP2_ START1_ EINT1 IM_DSP1_ START1_ EINT1 0007h R6235 (185Bh) IRQ1_Mask_28 00 000 000 00 000 IM_DSP3_ START2_ EINT1 IM_DSP2_ START2_ EINT1 IM_DSP1_ START2_ EINT1 0007h R6237 (185Dh) IRQ1_Mask_30 00 000 000 00 000 IM_DSP3_ BUSY_ EINT1 IM_DSP2_ BUSY_ EINT1 IM_DSP1_ BUSY_ EINT1 0007h R6238 (185Eh) IRQ1_Mask_31 00 000 000 00 000 00 IM_MIF1_ DONE_ EINT1 0001h R6239 (185Fh) IRQ1_Mask_32 00 000 000 00 000 00 IM_MIF1_ BLOCK_ EINT1 0001h R6272 (1880h) IRQ1_Raw_Status_1 0 0 0 CTRLIF_ ERR_ STS1 0 000 BOOT_ DONE_ STS1 0 000 000 0000h R6273 (1881h) IRQ1_Raw_Status_2 00 000 00 FLL1_ LOCK_ STS1 00 000 000 0000h R6278 (1886h) IRQ1_Raw_Status_7 00 000 000 00 0 MICD_ CLAMP_ STS1 0JD2_STS10 JD1_STS1 0000h R6280 (1888h) IRQ1_Raw_Status_9 00 000 000 00 000 0 DRC2_ SIG_DET_ STS1 DRC1_ SIG_DET_ STS1 0000h R6283 (188Bh) IRQ1_Raw_Status_12 00 000 000 0 SPKOUTL _SC_STS1 00 HP2R_ SC_STS1 HP2L_SC_ STS1 HP1R_ SC_STS1 HP1L_SC_ STS1 0000h R6284 (188Ch) IRQ1_Raw_Status_13 00 000 000 0 SPKOUTL _ENABLE_ DONE_ STS1 000 0 HP1R_ ENABLE_ DONE_ STS1 HP1L_ ENABLE_ DONE_ STS1 0000h R6285 (188Dh) IRQ1_Raw_Status_14 00 000 000 0 SPKOUTL _ DISABLE_ DONE_ STS1 000 0 HP1R_ DISABLE_ DONE_ STS1 HP1L_ DISABLE_ DONE_ STS1 0000h R6286 (188Eh) IRQ1_Raw_Status_15 0 0 0 0 0 0 0 0 0 0 0 0 0 SPK_ OVERHEA T_WARN_ STS1 SPK_ OVERHEA T_STS1 SPK_ SHUTDO WN_STS1 0000h R6288 (1890h) IRQ1_Raw_Status_17 GPIO16_ STS1 GPIO15_ STS1 GPIO14_ STS1 GPIO13_ STS1 GPIO12_ STS1 GPIO11_ STS1 GPIO10_ STS1 GPIO9_ STS1 GPIO8_ STS1 GPIO7_ STS1 GPIO6_ STS1 GPIO5_ STS1 GPIO4_ STS1 GPIO3_ STS1 GPIO2_ STS1 GPIO1_ STS1 0000h R6293 (1895h) IRQ1_Raw_Status_22 00 000 000 00 00 EVENT4_ NOT_ EMPTY_ STS1 EVENT3_ NOT_ EMPTY_ STS1 EVENT2_ NOT_ EMPTY_ STS1 EVENT1_ NOT_ EMPTY_ STS1 0000h R6294 (1896h) IRQ1_Raw_Status_23 00 000 000 00 00 EVENT4_ FULL_ STS1 EVENT3_ FULL_ STS1 EVENT2_ FULL_ STS1 EVENT1_ FULL_ STS1 0000h Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default |
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