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CS47L35 Datasheet(PDF) 268 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 268 Page - Cirrus Logic |
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268 / 300 page  268 DS1085F3 CS47L35 6 Register Map The 32-bit DSP register space is described in Table 6-2. R6550 (1996h) IRQ2_Raw_Status_23 00 000 000 00 00 EVENT4_ FULL_ STS2 EVENT3_ FULL_ STS2 EVENT2_ FULL_ STS2 EVENT1_ FULL_ STS2 0000h R6551 (1997h) IRQ2_Raw_Status_24 00 000 000 00 00 EVENT4_ WMARK_ STS2 EVENT3_ WMARK_ STS2 EVENT2_ WMARK_ STS2 EVENT1_ WMARK_ STS2 0000h R6552 (1998h) IRQ2_Raw_Status_25 00 000 000 00 000 DSP3_ DMA_ STS2 DSP2_ DMA_ STS2 DSP1_ DMA_ STS2 0000h R6557 (199Dh) IRQ2_Raw_Status_30 00 000 000 00 000 DSP3_ BUSY_ STS2 DSP2_ BUSY_ STS2 DSP1_ BUSY_ STS2 0000h R6662 (1A06h) Interrupt_Debounce_7 00 000 000 00 0 MICD_ CLAMP_ DB 0 JD2_DB 0 JD1_DB 0000h R6784 (1A80h) IRQ1_CTRL 01 00 IM_IRQ1 IRQ_POL IRQ_OP_ CFG 0 0 0 000 000 4400h R6786 (1A82h) IRQ2_CTRL 00 00 IM_IRQ2 000 00 000 000 0000h R6816 (1AA0h) Interrupt_Raw_Status_1 00 000 000 00 000 0 IRQ2_STS IRQ1_STS 0000h R6848 (1AC0h) GPIO_Debounce_Config 00 000 000 00 00 GP_DBTIME [3:0] 0000h R6864 (1AD0h) AOD_Pad_Ctrl 00 000 000 00 000 0 RESET_ PU RESET_ PD 0002h Table 6-2. Register Map Definition—32-bit region Register Name 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 Default R12288 (3000h) WSEQ_Sequence_1 WSEQ_DATA_WIDTH0 [2:0] WSEQ_ADDR0 [12:0] 82253719h WSEQ_DELAY0 [3:0] WSEQ_DATA_START0 [3:0] WSEQ_DATA0 [7:0] R12290 (3002h) WSEQ_Sequence_2 WSEQ_DATA_WIDTH1 [2:0] WSEQ_ADDR1 [12:0] C2300001h WSEQ_DELAY1 [3:0] WSEQ_DATA_START1 [3:0] WSEQ_DATA1 [7:0] R12292 (3004h) WSEQ_Sequence_3 WSEQ_DATA_WIDTH2 [2:0] WSEQ_ADDR2 [12:0] 02251301h WSEQ_DELAY2 [3:0] WSEQ_DATA_START2 [3:0] WSEQ_DATA2 [7:0] R12294 (3006h) WSEQ_Sequence_4 WSEQ_DATA_WIDTH3 [2:0] WSEQ_ADDR3 [12:0] 8225191Fh WSEQ_DELAY3 [3:0] WSEQ_DATA_START3 [3:0] WSEQ_DATA3 [7:0] R12296 (3008h) WSEQ_Sequence_5 WSEQ_DATA_WIDTH4 [2:0] WSEQ_ADDR4 [12:0] 82310B00h WSEQ_DELAY4 [3:0] WSEQ_DATA_START4 [3:0] WSEQ_DATA4 [7:0] R12298 (300Ah) WSEQ_Sequence_6 WSEQ_DATA_WIDTH5 [2:0] WSEQ_ADDR5 [12:0] E231023Bh WSEQ_DELAY5 [3:0] WSEQ_DATA_START5 [3:0] WSEQ_DATA5 [7:0] R12300 (300Ch) WSEQ_Sequence_7 WSEQ_DATA_WIDTH6 [2:0] WSEQ_ADDR6 [12:0] 02313B01h WSEQ_DELAY6 [3:0] WSEQ_DATA_START6 [3:0] WSEQ_DATA6 [7:0] R12302 (300Eh) WSEQ_Sequence_8 WSEQ_DATA_WIDTH7 [2:0] WSEQ_ADDR7 [12:0] 62300000h WSEQ_DELAY7 [3:0] WSEQ_DATA_START7 [3:0] WSEQ_DATA7 [7:0] R12304 (3010h) WSEQ_Sequence_9 WSEQ_DATA_WIDTH8 [2:0] WSEQ_ADDR8 [12:0] E2314288h WSEQ_DELAY8 [3:0] WSEQ_DATA_START8 [3:0] WSEQ_DATA8 [7:0] R12306 (3012h) WSEQ_Sequence_10 WSEQ_DATA_WIDTH9 [2:0] WSEQ_ADDR9 [12:0] 02310B00h WSEQ_DELAY9 [3:0] WSEQ_DATA_START9 [3:0] WSEQ_DATA9 [7:0] R12308 (3014h) WSEQ_Sequence_11 WSEQ_DATA_WIDTH10 [2:0] WSEQ_ADDR10 [12:0] 02310B00h WSEQ_DELAY10 [3:0] WSEQ_DATA_START10 [3:0] WSEQ_DATA10 [7:0] R12310 (3016h) WSEQ_Sequence_12 WSEQ_DATA_WIDTH11 [2:0] WSEQ_ADDR11 [12:0] 02250E01h WSEQ_DELAY11 [3:0] WSEQ_DATA_START11 [3:0] WSEQ_DATA11 [7:0] R12312 (3018h) WSEQ_Sequence_13 WSEQ_DATA_WIDTH12 [2:0] WSEQ_ADDR12 [12:0] 42310C02h WSEQ_DELAY12 [3:0] WSEQ_DATA_START12 [3:0] WSEQ_DATA12 [7:0] R12314 (301Ah) WSEQ_Sequence_14 WSEQ_DATA_WIDTH13 [2:0] WSEQ_ADDR13 [12:0] E2310227h WSEQ_DELAY13 [3:0] WSEQ_DATA_START13 [3:0] WSEQ_DATA13 [7:0] R12316 (301Ch) WSEQ_Sequence_15 WSEQ_DATA_WIDTH14 [2:0] WSEQ_ADDR14 [12:0] 02313B01h WSEQ_DELAY14 [3:0] WSEQ_DATA_START14 [3:0] WSEQ_DATA14 [7:0] R12318 (301Eh) WSEQ_Sequence_16 WSEQ_DATA_WIDTH15 [2:0] WSEQ_ADDR15 [12:0] E2314266h WSEQ_DELAY15 [3:0] WSEQ_DATA_START15 [3:0] WSEQ_DATA15 [7:0] R12320 (3020h) WSEQ_Sequence_17 WSEQ_DATA_WIDTH16 [2:0] WSEQ_ADDR16 [12:0] E2315294h WSEQ_DELAY16 [3:0] WSEQ_DATA_START16 [3:0] WSEQ_DATA16 [7:0] R12322 (3022h) WSEQ_Sequence_18 WSEQ_DATA_WIDTH17 [2:0] WSEQ_ADDR17 [12:0] 02310B00h WSEQ_DELAY17 [3:0] WSEQ_DATA_START17 [3:0] WSEQ_DATA17 [7:0] R12324 (3024h) WSEQ_Sequence_19 WSEQ_DATA_WIDTH18 [2:0] WSEQ_ADDR18 [12:0] 02310B00h WSEQ_DELAY18 [3:0] WSEQ_DATA_START18 [3:0] WSEQ_DATA18 [7:0] R12326 (3026h) WSEQ_Sequence_20 WSEQ_DATA_WIDTH19 [2:0] WSEQ_ADDR19 [12:0] E2251734h WSEQ_DELAY19 [3:0] WSEQ_DATA_START19 [3:0] WSEQ_DATA19 [7:0] R12328 (3028h) WSEQ_Sequence_21 WSEQ_DATA_WIDTH20 [2:0] WSEQ_ADDR20 [12:0] 0225F501h WSEQ_DELAY20 [3:0] WSEQ_DATA_START20 [3:0] WSEQ_DATA20 [7:0] R12330 (302Ah) WSEQ_Sequence_22 WSEQ_DATA_WIDTH21 [2:0] WSEQ_ADDR21 [12:0] 0000F000h WSEQ_DELAY21 [3:0] WSEQ_DATA_START21 [3:0] WSEQ_DATA21 [7:0] Table 6-1. Register Map Definition—16-bit region (Cont.) Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default |
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