DS0128 datasheet(26/140 Pages) MICROSEMI

26 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

2.3.4

Timing Model

This section describes timing model and timing parameters.

Figure 2 •

Timing Model

The following table lists the timing model parameters in worst commercial-case conditions when

TJ = 85 °C, VDD = 1.14 V.

Table 17 •

Timing Model Parameters

Index

Symbol

Description

–1

Unit

For More Information

ATPY

Propagation delay of DDR3 receiver

1.605

See Table 137, page 50

BTICLKQ

Clock-to-Q of the input data register

0.16

See Table 221, page 71

TISUD

Setup time of the input data register

0.357

See Table 221, page 71

CTRCKH

Input high delay for global clock

1.53

See Table 227, page 78

TRCKL

Input low delay for global clock

0.897

See Table 227, page 78

DTPY

Input propagation delay of LVDS

receiver

2.774

See Table 167, page 57

ETDP

Propagation delay of a three-input AND

gate

0.198

See Table 223, page 76

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