DS0128 datasheet(53/140 Pages) MICROSEMI

53 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

AC Switching Characteristics

Worst-case commercial conditions: TJ = 85 °C, VDD = 1.14 V, worst-case VDDI.

2.3.6.2 Stub-Series Terminated Logic

Stub-Series Terminated Logic (SSTL) for 2.5 V (SSTL2), 1.8 V (SSTL18), and 1.5 V (SSTL15) is

supported in IGLOO2 and SmartFusion2 SoC FPGAs. SSTL2 is defined by JEDEC standard JESD8-9B

and SSTL18 is defined by JEDEC standard JESD8-15. IGLOO2 SSTL I/O configurations are designed to

meet double data rate standards DDR/2/3 for general purpose memory buses. Double data rate

standards are designed to meet their JEDEC specifications as defined by JEDEC standard JESD79F for

DDR, JEDEC standard JESD79-2F for DDR, JEDEC standard JESD79-3D for DDR3, and JEDEC

standard JESD209A for LPDDR.

Table 101 • HSTL Receiver Characteristics for DDRIO I/O Bank with Fixed Code (Input Buffers)

On-Die Termination (ODT)

TPY

Unit

–1

–Std

Pseudo differential

None

1.605

1.888

47.8

1.614

1.898

True differential

None

1.622

1.909

47.8

1.628

1.916

Table 102 • HSTL Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)

TDP

TZL

TZH

THZ

TLZ

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

HSTL Class I

Single-ended 2.6

3.059

2.514

2.958

2.514

2.958

2.431

2.86

2.431

2.86

Differential

2.621

3.083

2.648

3.115

2.647

3.113

2.925

3.442

2.923

3.44

HSTL Class II

Single-ended 2.511

2.954

2.488

2.927

2.49

2.93

2.409

2.833

2.411

2.836

Differential

2.528

2.974

2.552

3.003

2.551

3.001

2.897

3.409

2.896

3.408

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