DS0128 datasheet(86/140 Pages) MICROSEMI

86 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

2.3.10.2 Timing Characteristics

The following table lists the combinatorial cell propagation delays in worst commercial-case conditions

when TJ = 85 °C, VDD = 1.14 V.

2.3.10.3 Sequential Module

IGLOO2 and SmartFusion2 SoC FPGAs offer a separate flip-flop which can be used independently from

the LUT. The flip-flop can be configured as a register or a latch and has a data input and optional enable,

synchronous load (clear or preset), and asynchronous load (clear or preset).

Figure 15 • Sequential Module

Table 223 • Combinatorial Cell Propagation Delays

Combinatorial Cell

Equation

Symbol

–1

–Std

Unit

INV

Y = !A

TPD

0.1

0.118

AND2

Y = A · B

TPD

0.164

0.193

NAND2

Y = !(A · B)

TPD

0.147

0.173

OR2

Y = A + B

TPD

0.164

0.193

NOR2

Y = !(A + B)

TPD

0.147

0.173

XOR2

Y = A

 B

TPD

0.164

0.193

XOR3

Y = A

 B  C

TPD

0.225

0.265

AND3

Y = A · B · C

TPD

0.209

0.246

AND4

Y = A · B · C · D

TPD

0.287

0.338

SLE

ALn

ADn

SLn

LAT

CLK

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