DS0128 datasheet(64/140 Pages) MICROSEMI

64 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

Table 154 • LPDDR-LVCMOS 1.8 V Minimum and Maximum AC Switching Speeds

Parameter

Symbol Max Unit Conditions

Maximum data rate (for DDRIO I/O bank)

DMAX

400 Mbps AC loading: 17pf load, 8 ma

drive and above/all slew

Table 155 • LPDDR-LVCMOS 1.8 V Calibrated Impedance Option

Parameter

Symbol

Typ

Unit

Supported output driver calibrated

impedance (for DDRIO I/O bank)

RODT_CAL

75, 60, 50, 33, 25, 20



Table 156 • LPDDR-LVCMOS 1.8 V AC Test Parameter Specifications

Parameter

Symbol

Typ

Unit

Measuring/trip point for data path

VTRIP

0.9

Resistance for enable path (TZH, TZL, THZ, TLZ)RENT



Capacitive loading for enable path (TZH, TZL, THZ, TLZ)

CENT

5pF

Capacitive loading for data path (TDP)

CLOAD

5pF

Table 157 • LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification for DDRIO Bank

Output Drive Selection

VOH (V)

Min

VOL (V)

Max

IOH (at VOH) mA

IOL (at VOL) mA

2 mA

VDDI – 0.45

0.45

4 mA

VDDI – 0.45

0.45

6 mA

VDDI – 0.45

0.45

8 mA

VDDI – 0.45

0.45

10 mA

VDDI – 0.45

0.45

12 mA

VDDI – 0.45

0.45

16 mA1

VDDI – 0.45

0.45

1. 16 mA Drive Strengths, All Slews, meet LPDDR JEDEC electrical compliance.

Table 158 • LPDDR-LVCMOS 1.8V AC Switching Characteristics for Receiver (for DDRIO

I/O Bank with Fixed Code - Input Buffers)

ODT (On Die

Termination)

–1

–Std

–1

–Std

Unit

None

1.968

2.315

2.099

2.47

Table 159 • LPDDR-LVCMOS 1.8 V AC Switching Characteristics for Transmitter for DDRIO I/O Bank (Output

and Tristate Buffers)

Output Drive

Selection

Slew

Control

TDP

TZL

TZH

THZ1

TLZ1

Unit

–1

–Std

–1

–Std

–1

–Std –1

–Std

–1

–Std

2 mA

slow

4.234

4.981 3.646

4.29

4.245

4.995 4.908

5.774 4.434

5.216 ns

medium

3.824

4.498 3.282

3.861 3.834

4.511 4.625

5.441 4.116

4.843 ns

medium_fast 3.627

4.267 3.111

3.66

3.637

4.279 4.481

5.272 3.984

4.687 ns

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