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DS0128 Datasheet(PDF) 89 Page - Microsemi Corporation |
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DS0128 Datasheet(HTML) 89 Page - Microsemi Corporation |
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89 / 140 page  IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 79 The following table lists the 010 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. The following table lists the 005 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. 2.3.12 FPGA Fabric SRAM See UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for more information. 2.3.12.1 FPGA Fabric Large SRAM (LSRAM) The following table lists the RAM1K18 – dual-port mode for depth × width configuration 1K × 18 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 229 • 010 Device Global Resource Parameter Symbol –1 –Std Unit Min Max Min Max Input low delay for global clock TRCKL 0.626 0.669 0.627 0.668 ns Input high delay for global clock TRCKH 1.112 1.182 1.308 1.393 ns Maximum skew for global clock TRCKSW 0.07 0.085 ns Table 230 • 005 Device Global Resource Parameter Symbol –1 –Std Unit Min Max Min Max Input low delay for global clock TRCKL 0.625 0.66 0.628 0.66 ns Input high delay for global clock TRCKH 1.126 1.187 1.325 1.397 ns Maximum skew for global clock TRCKSW 0.061 0.072 ns Table 231 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1K × 18 Parameter Symbol –1 –Std Unit Min Max Min Max Clock period TCY 2.5 2.941 ns Clock minimum pulse width high TCLKMPWH 1.125 1.323 ns Clock minimum pulse width low TCLKMPWL 1.125 1.323 ns Pipelined clock period TPLCY 2.5 2.941 ns Pipelined clock minimum pulse width high TPLCLKMPWH 1.125 1.323 ns Pipelined clock minimum pulse width low TPLCLKMPWL 1.125 1.323 ns Read access time with pipeline register TCLK2Q 0.334 0.393 ns Read access time without pipeline register 2.273 2.674 ns Access time with feed-through write timing 1.529 1.799 ns Address setup time TADDRSU 0.441 0.519 ns Address hold time TADDRHD 0.274 0.322 ns Data setup time TDSU 0.341 0.401 ns Data hold time TDHD 0.107 0.126 ns Block select setup time TBLKSU 0.207 0.244 ns |
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