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DS0128 Datasheet(PDF) 82 Page - Microsemi Corporation |
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DS0128 Datasheet(HTML) 82 Page - Microsemi Corporation |
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82 / 140 page ![]() IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 72 TDDRIWAL Asynchronous load minimum pulse width for input DDR F, F 0.304 0.357 ns TDDRICKMPWH Clock minimum pulse width high for input DDR B, B 0.075 0.088 ns TDDRICKMPWL Clock minimum pulse width low for input DDR B, B 0.159 0.187 ns Table 221 • Input DDR Propagation Delays (continued) Symbol Description Measuring Nodes (from, to) –1 –Std Unit |
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