DS0128 datasheet(87/140 Pages) MICROSEMI

87 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

The following figure shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous

clear) for a flip-flop (LAT = 0).

Figure 16 • Sequential Module Timing Diagram

2.3.10.3.1 Timing Characteristics

The following table lists the register delays in worst commercial-case conditions when TJ = 85 °C,

VDD = 1.14 V.

Table 224 • Register Delays

Parameter

Symbol

–1

–Std

Unit

Clock-to-Q of the core register

TCLKQ

0.108

0.127

Data setup time for the core register

TSUD

0.254

0.298

Data hold time for the core register

THD

Enable setup time for the core register

TSUE

0.335

0.394

Enable hold time for the core register

THE

Synchronous load setup time for the core register

TSUSL

0.335

0.394

Synchronous load hold time for the core register

THSL

Asynchronous Clear-to-Q of the core register (ADn = 1)

TALN2Q

0.473

0.556

Asynchronous preset-to-Q of the core register (ADn = 0)

0.451

0.531

Asynchronous load removal time for the core register

TREMALN

Asynchronous load recovery time for the core register

TRECALN

0.353

0.415

Asynchronous load minimum pulse width for the core register

TWALN

0.266

0.313

Clock minimum pulse width high for the core register

TCKMPWH

0.065

0.077

Clock minimum pulse width low for the core register

TCKMPWL

0.139

0.164

DS0128 Datasheet(PDF) 87 Page - Microsemi Corporation

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