DS0128 datasheet(33/140 Pages) MICROSEMI

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IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

2.3.5.5

Detailed I/O Characteristics

The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of

DDRIO I/O bank at VOH/VOL Level.

Table 24 •

Input Capacitance, Leakage Current, and Ramp Time

Symbol

Description

Maximum Unit

Conditions

CIN

Input capacitance

IIL (dc)

Input current low

(Applicable to HSTL/SSTL inputs only)

400

µA

VDDI = 2.5 V

500

µA

VDDI = 1.8 V

600

µA

VDDI = 1.5 V1

Applicable when I/O pair is programmed with an HSTL/SSTL I/O type on IOP and an un-

terminated I/O type (LVCMOS, for example) on ION pad.

Input current low

(Applicable to all other digital inputs)

µA

IIH (dc)

Input current high

(Applicable to HSTL/SSTL inputs only)

400

µA

VDDI = 2.5 V

500

µA

VDDI = 1.8 V

600

µA

VDDI = 1.5 V1

Input current high

(Applicable to all other digital inputs)

µA

TRAMPIN2

Voltage ramp must be monotonic.

Input ramp time

(Applicable to all digital inputs)

Table 25 •

I/O Weak Pull-up/Pull-down Resistances for DDRIO I/O Bank

VDDI Domain

R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at VOL (

Min

Max

Min

Max

2.5 V1, 2

R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX).

R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN).

10K

17.8K

9.98K

18K

1.8 V1, 2

10.3K

19.1K

10.3K

19.5K

1.5 V1, 2

10.6K

20.2K

10.6K

21.1K

1.2 V1, 2

11.1K

22.7K

11.2K

24.6K

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