DS0128 datasheet(56/140 Pages) MICROSEMI

56 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

2.3.6.4 Stub-Series Terminated Logic 1.8 V (SSTL18)

SSTL18 Class I and Class II are supported in IGLOO2 and SmartFusion2 SoC FPGAs, and also comply

with the reduced and full drive double date rate (DDR2) standard. IGLOO2 and SmartFusion2 SoC

FPGA I/Os support both standards for single-ended signaling and differential signaling for SSTL18. This

standard requires a differential amplifier input buffer and a push-pull output buffer.

Table 113 • DDR1/SSTL2 Receiver Characteristics for MSIOD I/O Bank (Input Buffers)

On-Die

Termination (ODT)

TPY

Unit

–1

–Std

Pseudo differential

None

2.476

2.913

True differential

None

2.475

2.911

Table 114 • SSTL2 Class I Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)

TDP

TZL

TZH

THZ

TLZ

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

Single-ended

2.26

2.66

1.99

2.341 1.985

2.335

2.135

2.512

2.13

2.505

Differential

2.26

2.658

2.202

2.591 2.201

2.589

2.393

2.815

2.392

2.814

Table 115 • DDR1/SSTL2 Class I Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)

TDP

TZL

TZH

THZ

TLZ

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

Single-ended

2.055

2.417

2.037

2.396 2.03

2.388

2.068

2.433

2.061

2.425

Differential

2.192

2.58

2.434

2.864 2.425

2.852

2.164

2.545

2.156

2.536

Table 116 • DDR1/SSTL2 Class I Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate

Buffers)

TDP

TZL

TZH

THZ

TLZ

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

Single-ended

1.512

1.779

1.462

1.72

1.462

1.72

1.676

1.972

1.676

1.971

Differential

1.676

1.971

1.774

2.087 1.766

2.077

1.854

2.181

1.845

2.171

Table 117 • DDR1/SSTL2 Class II Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate

Buffers)

TDP

TZL

TZH

THZ

TLZ

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

Single-ended

2.122

2.497

1.906

2.243 1.902

2.237

2.061

2.424

2.056

2.418

Differential

2.127

2.501

2.042

2.402 2.043

2.403

2.363

2.78

2.365

2.781

Table 118 • DDR1/SSTL2 Class II Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)

TDP

TZL

TZH

THZ

TLZ

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

Single-ended

2.29

2.693

1.988

2.338 1.978

2.326

1.989

2.34

1.979

2.328

Differential

2.418

2.846

2.304

2.711 2.297

2.702

2.131

2.506

2.124

2.499

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