DS0128 datasheet(34/140 Pages) MICROSEMI

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IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of

MSIO I/O bank at VOH/VOL Level.

The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of

MSIOD I/O bank at VOH/VOL Level.

The following table lists the hysteresis voltage value for schmitt trigger mode input buffers.

Table 26 •

I/O Weak Pull-Up/Pull-Down Resistances for MSIO I/O Bank

VDDI Domain

R(WEAK PULL-UP) at VOH ( R(WEAK PULL-DOWN) at VOL (

Min

Max

Min

Max

3.3 V

9.9K

17.1K

9.98K

17.5K

2.5 V1, 2

R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX).

R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN).

10K

17.6K

10.1K

18.4K

1.8 V1, 2

10.4K

19.1K

10.4K

20.4K

1.5 V1, 2

10.7K

20.4K

10.8K

22.2K

1.2 V1, 2

11.3K

23.2K

11.5K

26.7K

Table 27 •

I/O Weak Pull-up/Pull-down Resistances for MSIOD I/O Bank

VDDI Domain

R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at VOL ()

Min

Max

Min

Max

2.5 V1, 2

R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX).

R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN).

9.6K

16.6K

9.5K

16.4K

1.8 V1, 2

9.7K

17.3K

9.7K

17.1K

1.5 V1, 2

9.9K

18K

9.8K

17.6K

1.2 V1, 2

10.3K

19.6K

10K

19.1K

Table 28 •

Schmitt Trigger Input Hysteresis

Input Buffer Configuration

Hysteresis Value (Typical, unless otherwise noted)

3.3 V LVTTL/LVCMOS/

PCI/PCI-X

0.05 × VDDI (worst-case)

2.5 V LVCMOS

0.05 × VDDI (worst-case)

1.8 V LVCMOS

0.1 × VDDI (worst-case)

1.5 V LVCMOS

60 mV

1.2 V LVCMOS

20 mV

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