DS0128 datasheet(84/140 Pages) MICROSEMI

84 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

Figure 13 • Output DDR Timing Diagram

2.3.9.5 Timing Characteristics

The following table lists the output DDR propagation delays in worst commercial-case conditions when

TJ = 85 °C, VDD = 1.14 V.

Table 222 • Output DDR Propagation Delays

Symbol

Description

Measuring Nodes

(from, to)

–1

–Std

Unit

TDDROCLKQ

Clock-to-out of DDR for output DDR

E, G

0.263

0.309

TDDROSUDF

Data_F data setup for output DDR

F, E

0.143

0.168

TDDROSUDR

Data_R data setup for output DDR

A, E

0.19

0.223

TDDROHDF

Data_F data hold for output DDR

F, E

TDDROHDR

Data_R data hold for output DDR

A, E

TDDROSUE

Enable setup for input DDR

B, E

0.419

0.493

TDDROHE

Enable hold for input DDR

B, E

TDDROSUSLN

Synchronous load setup for input DDR

D, E

0.196

0.231

TDDROHSLN

Synchronous load hold for input DDR

D, E

TDDROAL2Q

Asynchronous load-to-out for output DDR

C, G

0.528

0.621

TDDROREMAL

Asynchronous load removal time for output DDR

C, E

TDDRORECAL

Asynchronous load recovery time for output DDR

C, E

0.034

0.04

DS0128 Datasheet(PDF) 84 Page - Microsemi Corporation

DS0128 Datasheet(HTML) 84 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL