DS0128 datasheet(77/140 Pages) MICROSEMI

77 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

The following table lists the input data register propagation delays in worst commercial-case conditions

when TJ = 85 °C, VDD = 1.14 V.

Table 219 • Input Data Register Propagation Delays

Parameter

Symbol

Measuring

Nodes

(from, to)1

For the derating values at specific junction temperature and voltage supply levels, see Table 16, page 15 for derating values.

–1

–Std

Unit

Bypass delay of the input register

TIBYP

F, G

0.353

0.415 ns

Clock-to-Q of the input register

TICLKQ

E, G

0.16

0.188 ns

Data setup time for the input register

TISUD

A, E

0.357

0.421 ns

Data hold time for the input register

TIHD

A, E

Enable setup time for the input register

TISUE

B, E

0.46

0.542 ns

Enable hold time for the input register

TIHE

B, E

Synchronous load setup time for the input register

TISUSL

D, E

0.46

0.542 ns

Synchronous load hold time for the input register

TIHSL

D, E

Asynchronous clear-to-Q of the input register (ADn=1)

TIALN2Q

C, G

0.625

0.735 ns

Asynchronous preset-to-Q of the input register (ADn=0)

C, G

0.587

0.69

Asynchronous load removal time for the input register

TIREMALN

C, E

Asynchronous load recovery time for the input register

TIRECALN

C, E

0.074

0.087 ns

Asynchronous load minimum pulse width for the input register

TIWALN

C, C

0.304

0.357 ns

Clock minimum pulse width high for the input register

TICKMPWH

E, E

0.075

0.088 ns

Clock minimum pulse width low for the input register

TICKMPWL

E, E

0.159

0.187 ns

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