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DS0128 Datasheet(PDF) 91 Page - Microsemi Corporation |
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DS0128 Datasheet(HTML) 91 Page - Microsemi Corporation |
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91 / 140 page  IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 81 The following table lists the RAM1K18 – dual-port mode for depth × width configuration 4K × 4 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Address setup time TADDRSU 0.475 0.559 ns Address hold time TADDRHD 0.274 0.322 ns Data setup time TDSU 0.336 0.395 ns Data hold time TDHD 0.082 0.096 ns Block select setup time TBLKSU 0.207 0.244 ns Block select hold time TBLKHD 0.216 0.254 ns Block select to out disable time (when pipelined register is disabled) TBLK2Q 1.529 1.799 ns Block select minimum pulse width TBLKMPW 0.186 0.219 ns Read enable setup time TRDESU 0.485 0.57 ns Read enable hold time TRDEHD 0.071 0.083 ns Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU 0.248 0.291 ns Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD 0.102 0.12 ns Asynchronous reset to output propagation delay TR2Q 1.514 1.781 ns Asynchronous reset removal time TRSTREM 0.506 0.595 ns Asynchronous reset recovery time TRSTREC 0.004 0.005 ns Asynchronous reset minimum pulse width TRSTMPW 0.301 0.354 ns Pipelined register asynchronous reset removal time TPLRSTREM –0.279 –0.328 ns Pipelined register asynchronous reset recovery time TPLRSTREC 0.327 0.385 ns Pipelined register asynchronous reset minimum pulse width TPLRSTMPW 0.282 0.332 ns Synchronous reset setup time TSRSTSU 0.226 0.265 ns Synchronous reset hold time TSRSTHD 0.036 0.043 ns Write enable setup time TWESU 0.415 0.488 ns Write enable hold time TWEHD 0.048 0.057 ns Maximum frequency FMAX 400 340 MHz Table 233 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4K × 4 Parameter Symbol –1 –Std Unit Min Max Min Max Clock period TCY 2.5 2.941 ns Clock minimum pulse width high TCLKMPWH 1.125 1.323 ns Clock minimum pulse width low TCLKMPWL 1.125 1.323 ns Pipelined clock period TPLCY 2.5 2.941 ns Pipelined clock minimum pulse width high TPLCLKMPWH 1.125 1.323 ns Table 232 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2K × 9 (continued) Parameter Symbol –1 –Std Unit Min Max Min Max |
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