DS0128 datasheet(27/140 Pages) MICROSEMI

27 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

FTDP

Propagation delay of an OR gate

0.179

See Table 223, page 76

GTDP

Propagation delay of an LVDS

transmitter

2.136

See Table 169, page 57

HTDP

Propagation delay of a three-input XOR

Gate

0.241

See Table 223, page 76

ITDP

Propagation delay of LVCMOS 2.5 V

transmitter, drive strength of 16 mA on

the MSIO bank

2.412

See Table 46, page 28

JTDP

Propagation delay of a two-input NAND

gate

0.179

See Table 223, page 76

KTDP

Propagation delay of LVCMOS 2.5 V

transmitter, drive strength of 8 mA on

the MSIO bank

2.309

See Table 46, page 28

LTCLKQ

Clock-to-Q of the data register

0.108

See Table 224, page 77

TSUD

Setup time of the data register

0.254

See Table 224, page 77

MTDP

Propagation delay of a two-input AND

gate

0.179

See Table 223, page 76

NTOCLKQ

Clock-to-Q of the output data register

0.263

See Table 220, page 69

TOSUD

Setup time of the output data register

0.19

See Table 220, page 69

OTDP

Propagation delay of SSTL2, Class I

transmitter on the MSIO bank

2.055

See Table 114, page 46

PTDP

Propagation delay of LVCMOS 1.5 V

transmitter, drive strength of 12 mA,

fast slew on the DDRIO bank

3.316

See Table 70, page 35

Table 17 •

Timing Model Parameters (continued)

Index

Symbol

Description

–1

Unit

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