AMD-766AC datasheet(33/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

5.2

PCI-ISA Bridge Configuration Registers (C0Axx)

These registers are in PCI configuration space, function 0. See section 5.1.2 for a description of the register naming

convention.

C0A00: PCI-ISA Bridge Vendor And Device ID

Configuration space; function 0; offset: 03-00h. Default: 7410 1022h. Read only.

31:16

15:0

DID

VID

VID. Vendor ID.

DID. PCI-ISA/LPC bridge device ID.

C0A04: PCI-ISA Bridge Status And Command Register

Configuration space; function 0; offset: 07-04h. Default: 0200 000Fh.

31:16

15:0

STATUS[15:0]

COMMAND[15:0]

COMMAND[2:0] IO, memory and master enable. Read only. Hardwired in the enabled state.

COMMAND[3] Special Cycle Enable, SPCYCEN. Read-write. 1=The IC responds to PCI shutdown special

cycles by generating a pulse over either CPURST# or INIT# (based on the state of C0A47[CPURS]). 0=The IC

ignores PCI shutdown special cycles.

COMMAND[15:4]. Read only. These bits are fixed at their default values.

STATUS[11:0]. Read only. These bits are fixed at their default values.

STATUS[12] Received Target Abort, RTGTABT. Read; set by hardware; write 1 to clear. 1=The PCI-ISA bridge

received a target abort while master of the PCI bus.

STATUS[13] Received Master Abort, RMASABT. Read; set by hardware; write 1 to clear. 1=The PCI-ISA

bridge received a master abort while master of the PCI bus.

STATUS[15:14]. Read only. These bits are fixed at their default values.

C0A08: PCI-ISA Bridge Revision And Class Code Register

Configuration space; function 0; offset: 0B-08h. Default: 0601 0001h. Read only.

31:8

7:0

CLASSCODE

REVISION

REVISION. PCI-ISA bridge silicon revision.

CLASSCODE. Provides the bridge class code as defined in the PCI specification.

C0A0C: PCI-ISA Bridge BIST-Header-Latency-Cache Register

Configuration space; function 0; offset: 0F-0Ch. Default: 0080 0000h. Read only.

31:24

23:16

15:8

7:0

BIST

HEADER

LATENCY

CACHE

CACHE, LATENCY, HEADER, BIST. These bits are fixed at their default values.

C0A2C: PCI-ISA Bridge Subsystem ID and Subsystem Vendor ID Register

Configuration space; function 0; offset: 2F-2Ch. Default: 0000_0000h. Read only.

31:16

15:0

SSID

SSVENDORID

SSVENDORID and SSID. Subsystem vendor ID and subsystem ID registers. This register is write accessible

through C0A70.

AMD-766AC Datasheet(PDF) 33 Page - Advanced Micro Devices

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