AMD-766AC datasheet(12/96 Pages) AMD

12 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

GPIO[31:17, 9, 2]. General purpose IO pins. See section 4.6.5 for details

about these pins. All GPIO pins are configured by PM[FF:F4 and D3:C0]

where the default function is specified. GPIO pins remain functional

during sleep states.

MSIRQ. Mouse interrupt request output (alternate function to GPIO17;

selected by PMD1). This is the mouse IRQ from the USB keyboard

emulation logic.

PNPIRQ[2:0]. Plug and play interrupt request [2:0] inputs (alternate

function to GPIO[20:18]; selected by PM[F4, D3, D2]). These may be

assigned to control the IRQ signals to the interrupt routing table shown in

section 4.3.2. They are controlled by C3A44.

BMREQ#. PCI bus master request input (alternate function to GPIO21;

selected by PMF5). This is intended to be the OR of the external PCI bus

request signals. If this function is selected by PMF5, then it controls the

PM00[BM_STS] status bit (if not, then IRQ[11:9, 7:3] are selected to be

the PCI REQ# signals). BMREQ# is treated as an asynchronous input.

PNPCS[1:0]#. Plug and play chip select [1:0] outputs (alternate function

to GPIO[23:22]; selected by PM[F7:F6]). These are programmable chip

select for external ISA bus devices. They becomes active during ISA bus

cycles to memory space or IO space as specified by C3A46[CS[1:0]MEM

and CS[1:0]IO]. They are valid for at least 1 PCLK cycle before and after

the ISA-bus command signal (IOR#, IOW#, MEMR#, or MEMW#).

PNPCS1#. Output; plug and play chip select 1 (alternate function to

GPIO23; selected by PMF7). This is designed to be a programmable chip

select to external ISA bus devices. It becomes active during ISA bus

cycles to memory space or IO space as specified by C3A46[CS1MEM and

CS1IO]. It is guaranteed to be valid before and after the ISA-bus

command signal.

VDD3

Functio

nal

INTIRQ8#. Real time clock interrupt output. This is the interrupt output

from the IC’s real-time clock. This pin may also be configured as GPIO16

by PMD0.

SQWAVE. Square wave clock output (alternate function to INTIRQ8#;

selected by PMD0). This is a square wave output, the frequency for which

is specified by C3A4E.

Output,

VDD3

High

Func.

INTRUDER#. Intruder detection. This controls PM46[INTRDR_STS].

This pin is not 5-volt tolerant.

Input

VDD_

Input

PCISTOP#. PCI bus clock stop output. This may be used to control the

system clock chip to control the PCI bus clock signals. It is controlled by

C3A50. This pin may also be configured as GPIO7 by PMC7.

VDD3

High

Func.

PME#. Power management interrupt. This pin may be used to generate

SMI or SCI interrupts and resume events. It controls PM20[PME_STS].

Input

VDD_

AUX

---

PRDY. Processor ready. When this is asserted, the IC freezes the timers

specified by C3A4C.

Input,

VDD3

PWRBTN#. Power button. This may be used to control the automatic

transition from a sleep state to FON. It controls PM00[PWRBTN_STS].

Also, if it is asserted for four seconds from any state other than SOFF, then

Input

VDD_

AUX

---

AMD-766AC Datasheet(PDF) 12 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 12 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL