AMD-766AC datasheet(65/96 Pages) AMD

65 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

C3A60: System Management Class Code Write Register

Configuration space; function 3; offset: 63-60h. Default: 0000_0000h. Read-write.

31:8

7:0

CCWRITE

Reserved

CCWRITE. The value placed in this register is visible in C3A08[CLASSCODE].

C3AA0: Serial Port Trap Address Register

Configuration space; function 3; offset: A3-A0h. Default: 02F8_03F8h. Read-write.

C3AA0 along with C3AA4 specify the address for COMA and COMB trap events. These events may be used to

generate an SMIs or SCIs or reload the system inactivity timer. The COMA and COMB trap events occur when the

following equations are true:

COMA trap event: AD[15:0] | MASKCA == ADDRCA | MASKCA;

COMB trap event: AD[15:0] | MASKCB == ADDRCB | MASKCB;

Where AD is the address phase of a PCI bus IO cycle. It is not necessary for the cycle to be targeted at the IC. The

mask bits cover of bits[7:0] .

31:16

15:0

ADDRCB

ADDRCA

ADDRCA and ADDRCB. Address for the COMA and COMB trap events.

C3AA4: Serial Port Trap Mask Register

Configuration space; function 3; offset: A5-A4h. Default: 0F0Fh. Read-write.

15:8

7:0

MASKCB

MASKCA

MASKCA and MASKCB. Address mask for the COMA and COMB trap events. See C3AA0 for details.

C3AA8: Audio Port 1 and 2 Trap Address Register

Configuration space; function 3; offset: AB-A8h. Default: 0330_0220h. Read-write.

C3AA8, C3AAC, and C3AB0 combine to specify the audio trap event. This event may be used to generate an SMIs

or SCIs or reload the system inactivity timer. The audio trap event occurs when the following equation is true:

Audio trap event:

(AD[15:0] | MASKAUD1 == ADDRAUD1 | MASKAUD1) & (PCI IO space access)

| (AD[15:0] | MASKAUD2 == ADDRAUD2 | MASKAUD2) & (PCI IO space access)

| (AD[15:0] | MASKAUD3 == ADDRAUD3 | MASKAUD3) & (PCI IO space access)

| (AD[15:0] | MASKAUD4 == ADDRAUD4 | MASKAUD4) & (PCI IO space access);

Where AD is the address phase of a PCI bus IO cycle. It is not necessary for the cycle to be targeted at the IC. The

mask bits cover bits[7:0] .

31:16

15:0

ADDRAUD2

ADDRAUD1

ADDRAUD1 and ADDRAUD2. Address for the audio trap events 1 and 2.

C3AAC: Audio Port 3 and 4 Trap Address Register

Configuration space; function 3; offset: AF-ACh. Default: 0388_0530h. Read-write.

31:16

15:0

ADDRAUD4

ADDRAUD3

ADDRAUD3 and ADDRAUD4. Address for the audio trap events 3 and 4. See C3AA8 for details.

AMD-766AC Datasheet(PDF) 65 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 65 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL