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AMD-766AC Datasheet(PDF) 57 Page - Advanced Micro Devices

Part # AMD-766AC
Description  Peripheral Bus Controller
PDF  96 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 57 Page - Advanced Micro Devices

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Preliminary Information
23167B – March 2001
AMD-766
TM Peripheral Bus Controller Data Sheet
57
5.7
USB Host Controller Memory-Mapped Registers
5.7.1
Summary
For a complete description of these registers, see the OCHI 1.0a specification.
Offset
Register
Offset
Register
00-03h
HcRevision
34-37h
HcFmInterval
04-07h
HcControl
38-3Bh
HcFrameRemaining
08-0Bh
HcCommandStatus
3C-3Fh
HcFmNumber
0C-0Fh
HcInterruptStatus
40-43h
HcPeriodicStart
10-13h
HcInterruptEnable
44-47h
HcLSThreshold
14-17h
HcInterruptDisable
48-4Bh
HcRhDescriptorA
18-1Bh
HcHCCA
4C-4Fh
HcRhDescriptorB
1C-1Fh
HcPeriodCurrentED
50-53h
HcRhStatus
20-23h
HcControlHeadED
54-57h
HcRhPortStatus[1]
24-27h
HcControlCurrentED
58-5Bh
HcRhPortStatus[2]
28-2Bh
HcBulkHeadED
5C-5Fh
HcRhPortStatus[3]
2C-2Fh
HcBulkCurrentED
60-63h
HcRhPortStatus[4]
30-33h
HcDoneHead
100h
HceControl
104h
HceInput
108h
HceOutput
10Ch
HceStatus
5.7.2
Implementation-Specific Items
•
HcRevision[7:0] is 10h to indicate that it conforms to OHCI 1.0.
•
HcRevision[8] is 1 to indicate that legacy keyboard & mouse emulation support is present.
•
HcFmInterval_FSLargestDataPacket resets to 0.
•
HcRhDescriptorA_NumberDownstreamPorts is hardwired to 4.
•
HcRhDescriptorA_NoPowerSwitching resets to 1.
•
HcRhDescriptorA_PowerSwitchingMode and HcRhDescriptorA_OverCurrentProtectionMode must not be set
and reset to 0.
•
HcRhDescriptorA_PowerOnToPowerGoodTime resets to 1 (representing 2 ms), and can only hold the values 0 to
3 (0 to 6 ms).
•
HcRhDescriptorA_NoOverCurrentProtection resets to 0.
•
HcRhDescriptorB_DeviceRemovable resets to 0 and should be set by BIOS if non-removable devices are
attached.
•
HcRhDescriptorB_PortPowerControlMask resets to 0 and should not be set.
•
Because power switching is not implemented, the set and clear power bits in HcRhStatus and HcRhPortStatus[1-
4] are not supported.
•
HceControl and HceStatus reset to 00h.
•
HceInput and HceOutput are not reset.
•
HcDoneHd[31:4] should not be modified.
•
HcFmInterval_FSLargestDataPacket is limited to 14 bits. Bit 15 is read-only 0.
•
HcFmNumber should not be modified.



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