AMD-766AC datasheet(70/96 Pages) AMD

70 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PM08: ACPI Power Management Timer

IO mapped (base pointer: C3A58); offset: 0B-08h. Default: 0000 0000h. Read only.

This is either a 24- or a 32-bit counter, based on the state of C3A41[3]. It is a free-running, incrementing counter

clocked off of a 3.579545 MHz clock. It does not count when in the system is in MOFF, SOFF, STD, or STR state.

When the MSB toggles (either bit[23] or bit[31]) then PM00[TMR_STS] is set. This timer is asynchronously cleared

when C3A41[TMRRST] is high.

31:24

23:0

ETM_VAL

TMR_VAL

TMR_VAL. Timer value. This provides the current count of the ACPI power management timer.

ETM_VAL. Extended timer value. If C3A41[3] is high, then these are the 8 MSBs of the ACPI power management

timer. If C3A41[3] is low, then this field always reads back as all zeros.

PM10: Processor Clock Control Register

IO mapped (base pointer: C3A58); offset: 13-10h. Default: 0000 0000h. Read-write.

31:5

3:1

Reserved

NTH_EN

NTH_RATIO

Reserved

NTH_RATIO. Normal throttling duty cycle. These specify the duty cycle of the STPCLK# signal to the processor

when the system is in normal throttling mode, enabled by NTH_EN. The field is encoded as follows:

RATIO bits

Description

RATIO bits

Description

000b

Reserved.

100b

50.0% STPCLK# active.

001b

87.5% STPCLK# active.

101b

37.5% STPCLK# active.

010b

75.0% STPCLK# active.

110b

25.0% STPCLK# active.

011b

62.5% STPCLK# active.

111b

12.5% STPCLK# active.

NTH_EN. Normal throttling enable. 1=Normal throttling (duty cycle specified by NTH_RATIO) is enabled.

Normal throttling is lower priority than thermal throttling (as specified by C3A50); when thermal throttling is

enabled, the throttling duty cycle is specified by C3A50. Throttling is disabled when in the C2, C3, POS, STR, STD,

or SOFF states. 0=Normal throttling is not enabled.

PM14: Processor Level 2 Register

IO mapped (base pointer: C3A58); offset: 14h. Default: 00h. Read only.

7:0

P_LVL2

P_LVL2. Reads from this register initiate the transition of the processor to the C2 state, as specified by C3A50.

This register is byte readable only. Reads from this register always return 00h.

PM15: Processor Level 3 Register

IO mapped (base pointer: C3A58); offset: 15h. Default: 00h. Read only.

7:0

P_LVL3

P_LVL3. Reads from this register initiate the transition of the processor to the C3 state, as specified by C3A50.

This register is byte readable only. Reads from this register always return 00h.

AMD-766AC Datasheet(PDF) 70 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 70 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL