AMD-766AC datasheet(86/96 Pages) AMD

86 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PME4: SMBus Host Address Register

IO mapped (base pointer: C3A58); offset: E5-E4h. Default: 0000h. Read-write.

15:8

7:1

HST10BA

HSTADDR

READCYC

READCYC. Host read (high) write (low) cycle. 1=Specifies that the cycle generated by a write to PM02[HOSTST]

is a read or receive command. 0=Cycle is a write or send command.

HSTADDR. Host cycle address. This specifies the 7-bit address to the SMBus generated by the host (as a master)

during SMBus cycles that are initiated by PME02[HOSTST].

HST10BA. Host 10-bit address LSBs. This field stores the second byte of the address, used in 10-bit SMBus host-

as-master transfers. If HSTADDR == 1111_0xxb, then the cycle is specified to use 10-bit addressing. If HSTADDR

is any other value, then HST10BA is not utilized.

PME6: SMBus Host Data Register

IO mapped (base pointer: C3A58); offset: E7-E6h. Default: 0000h. Read-write.

15:0

HSTDATA

HSTDATA. Host cycle data. This register is written to by software to specify the data to be passed to the SMBus

during write and send cycles. It is read by software to specify the data passed to host controller by the SMBus during

read and receive cycles. Bit[0] specifies the data written or read during the quick command cycle. Bits[7:0] specify

the data for byte read and write cycles, send byte cycles, and receive byte cycles. Bits[15:0] are used for word read

and write cycles and process calls. Bits[5:0] are used to specify the count for block read and write cycles.

PME8: SMBus Host Command Field Register

IO mapped (base pointer: C3A58); offset: E8h. Default: 00h. Read-write.

7:0

HSTCMD

HSTCMD. Host cycle command. This specifies the command field passed to the SMBus by the host controller

during read byte, write byte, read word, write word, process call, block read, and block write cycles. Host cycles are

initiated by PME2[HOSTST].

PME9: SMBus Host Block Data FIFO Access Port

IO mapped (base pointer: C3A58); offset: E9h. Default: 00h.

7:0

HSTFIFO

HSTFIFO. Host block read-write FIFO. For block write commands, software writes 1 to 32 bytes into this port

before sending them to the SMBus via the PME2[HOSTST] command. For block read commands, software read 1 to

32 bytes from this port after the block read cycle is complete. If, during a block read or write, an error occurs, then

the FIFO is flushed by the hardware. Read and write accesses to this port while the host is busy (PME0[HST_BSY])

are ignored.

PMEA: SMBus Host-As-Slave Data Register

IO mapped (base pointer: C3A58); offset: EB-EAh. Default: 0000h. Read only.

This register resides on the VDD_AUX power plane.

15:0

HSLVDATA

HSLVDATA. Host-as-slave data. When the SMBus logic determines that the current SMBus cycle is directed to the

host’s slave logic (because the address matches PMEE), then the data targeted to the IC during the cycle is latched in

this register. Also, if the address matches the snoop address in PMEF, then the cycle is assumed to be a write word

and the data is stored in this register.

AMD-766AC Datasheet(PDF) 86 Page - Advanced Micro Devices

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