AMD-766AC datasheet(69/96 Pages) AMD

69 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PM02: Power Management 1 Enable Register

IO mapped (base pointer: C3A58); offset: 03-02h. Default: 0000h. Read-write.

These bits work in conjunction with the corresponding bits in PM00 to generate SCI or SMI interrupts.

15:11

Reserved

RTC_EN

SLPBTN_EN

PWRBTN_EN

7:6

4:1

Reserved

GBL_EN

Reserved

TMR_EN

TMR_EN. ACPI timer SCI enable. 1=Enable an SCI interrupt when PM00[TMR_STS] is set high. Note: This

results in an SCI interrupt, regardless as to the state of PM04[SCI_EN].

GBL_EN. Global SCI enable. 1=Enable an SCI interrupt when PM00[GBL_STS] is set high. Note: This results in

an SCI interrupt, regardless as to the state of PM04[SCI_EN].

PWRBTN_EN. Power button SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state of

PM04[SCI_EN]) when PM00[PWRBTN_STS] is set high.

SLPBTN_EN. Sleep button SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state of

PM04[SCI_EN]) when PM00[SLPBTN_STS] is set high.

RTC_EN. Real time clock alarm SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state

of PM04[SCI_EN]) when PM00[RTC_STS] is set high.

PM04: Power Management 1 Control Register

IO mapped (base pointer: C3A58); offset: 05-04h. Default: 0000h.

15:14

12:10

9:3

Reserved

SLP_EN

SLP_TYP

Reserved

GBL_RLS

BM_RLD

SCI_EN

SCI_EN. SCI-SMI select. Read-write. Selects the type of interrupt generated by power management events.

SMI interrupt.

SCI interrupt.

Certain power management events may be programmed individually to generate SMI interrupts independent of the

state of this bit. Also, TMR_STS and GBL_STS always generate SCI interrupts regardless as to the state of this bit.

See section 4.6.1.1 for details.

BM_RLD. Bus master reload. Read-write. 1=Enables PM00[BM_STS] to resume from C3.

GBL_RLS. Global release. Read; write 1 to set; cleared by hardware. When this bit is set high, the hardware sets

PM28[BIOS_STS] high. GBL_RLS is cleared by the hardware when PM28[BIOS_STS] is cleared by software.

SLP_TYP. Sleep type. Read-write. Specifies the type of sleep state the system enters when SLP_EN is set high.

FON, S0. Full on.

POS, S1. Power on suspend.

2-4

Reserved.

STR, S3. Suspend to RAM.

STD, S4. Suspend to disk.

SOFF, S5. Soft off.

SLP_EN. Sleep enable. Write 1 only; reads back as 0. Writing a 1 to this bit causes the system to sequence into the

sleep state specified by SLP_TYP.

AMD-766AC Datasheet(PDF) 69 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 69 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL