AMD-766AC datasheet(67/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

C3AC4: Programmable IO Range Monitor 1 and 2 Trap Address Register

Configuration space; function 3; offset: C7-C4h. Default: 0000_0000h. Read-write.

C3AC4, C3AC8, and C3ACC combine to define the programmable IO range monitor trap events (PIORM[4:1]).

These events may be used to generate an SMIs or SCIs or reload the system inactivity timer. The trap events occurs

following equations are true:

PIORM1:

(AD[15:0] | MASKIO1 == ADDRIO1 | MASKIO1) & (PCI IO space access);

PIORM2:

(AD[15:0] | MASKIO2 == ADDRIO2 | MASKIO2) & (PCI IO space access);

PIORM3:

(AD[15:0] | MASKIO3 == ADDRIO3 | MASKIO3) & (PCI IO space access);

PIORM4:

(AD[15:0] | MASKIO4 == ADDRIO4 | MASKIO4) & (PCI IO space access);

Where AD is the address phase of a PCI bus IO cycle. It is not necessary for the cycle to be targeted at the IC. The

mask bits cover bits[7:0]. See C3A46[CS1UMB,CS0UMB] for a description of how the mask bits for programmable

IO range monitors 3 and 4 can be extended to bits[10:8].

31:16

15:0

ADDRIO2

ADDRIO1

ADDRIO1 and ADDRIO2. Address for the PIORM[1,2] trap events.

C3AC8: Programmable IO Range Monitor 3 and 4 Trap Address Register

Configuration space; function 3; offset: CB-C8h. Default: 0000_0000h. Read-write.

31:16

15:0

ADDRIO4

ADDRIO3

ADDRIO3 and ADDRIO4. Address for the PIORM[3,4] trap events. See C3AC4 for details.

C3ACC: Programmable IO Range Monitor Trap Mask Register

Configuration space; function 3; offset: CF-CCh. Default: 0000_0000h. Read-write.

31:24

23:16

15:8

7:0

MASKIO4

MASKIO3

MASKIO2

MASKIO1

MASKIO[4:1]. Address masks for the PIORM[4:1] trap events. See C3AC4 for details.

C3AD0: Programmable Memory Range Monitor 1 Trap Address Register

Configuration space; function 3; offset: D3-D0h. Default: 0000_0000h. Read-write.

C3AD0, C3AD4, and C3AD8 combine to define the address for the programmable memory range monitor 1 and 2

trap events (PMEMRM[1,2]). These events may be used to generate an SMIs or SCIs or reload the system inactivity

timer. These trap events occur when the following equations are true:

PMEMRM1: (AD[31:8] | MASKMEM1) == (ADDRMEM1 | MASKMEM1);

PMEMRM2: (AD[31:8] | MASKMEM2) == (ADDRMEM2 | MASKMEM2);

Where AD is the address phase of a PCI bus memory cycle. It is not necessary for the cycle to be targeted at the IC.

The mask bits cover bits[23:8].

31:8

7:0

ADDRMEM1

Reserved

ADDRMEM1. Memory address for the PMEMRM1 trap event.

C3AD4: Programmable Memory Range Monitor 2 Trap Address Register

Configuration space; function 3; offset: D7-D4h. Default: 0000_0000h. Read-write.

31:8

7:0

ADDRMEM2

Reserved

ADDRMEM2. Memory address for the PMEMRM2 trap event. See C3AD0 for details.

AMD-766AC Datasheet(PDF) 67 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 67 Page - Advanced Micro Devices

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