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AMD-766AC Datasheet(PDF) 35 Page - Advanced Micro Devices |
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AMD-766AC Datasheet(HTML) 35 Page - Advanced Micro Devices |
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35 / 96 page  Preliminary Information 23167B – March 2001 AMD-766 TM Peripheral Bus Controller Data Sheet 35 C0A41: ISA Bus Control 2 Register Configuration space; function 0; offset: 41h Default: 02h 76 54 321 0 MBL Reserved P92FR Reserved Reserved Reserved NMIDIS SHEN SHEN. Shadow register access enable. Read-write. 1=Shadowed IO access to legacy write-only registers is enabled. 0=Normal access of legacy registers. The following table specifies all registers affected by this bit: IO port R/W Normal mode Shadow mode DMA: 00h, 02h, 04h, 06h, W Base address for DMA channel Current address for DMA channel C0h, C4h, C8h, CCh R Current address for DMA channel Base address for DMA channel DMA: 01h, 03h, 05h, 07h, W Base byte count for DMA channel Current byte count for DMA channel C2h, C6h, CAh, CEh R Current byte count for DMA channel Base byte count for DMA channel DMA: 08h/D0h W Command Register DMA CH[3:0]/[7:4] Status Register DMA CH[3:0]/[7:4] R Status Register DMA CH[3:0]/[7:4] 1 st read: Command reg DMA CH[3:0]/[7:4] 2 nd read: Request reg DMA CH[3:0]/[7:4] 3 rd read: Mode register DMA CH0/4 4 th read: Mode register DMA CH1/5 5 th read: Mode register DMA CH2/6 6 th read: Mode register DMA CH3/7 DMA: 09h/D2h, 0Ah/D4h, 0Bh/D6h W See DMA controller Reserved DMA: 0Ch/D8h, 0Dh/DAh, 0Eh/DCh W See DMA controller Same as normal mode DMA: 0Fh/Deh W Write all masks [3:0]/[7:4] Write all masks [3:0]/[7:4] R Reserved Read all masks [3:0]/[7:4] PIT: 40h R Status byte counter 0 1 st read: Status byte counter 0 2 nd read: CRL for counter 0 3 rd read: CRM for counter 0 4 th read: CRL for counter 1 5 th read: CRM for counter 1 6 th read: CRL for counter 2 7 th read: CRM for counter 2 PIT: 41h R Status byte counter 1 Status byte counter 1 PIT: 42h R Status byte counter 2 Status byte counter 2 PIC: 20h R Interrupt request register for PIC 1 1 st read: ICW1 for controller 1 2 nd read: ICW2 for controller 1 3 rd read: ICW3 for controller 1 4 th read: ICW4 for controller 1 5 th read: OCW1 for controller 1 6 th read: OCW2 for controller 1 7 th read: OCW3 for controller 1 8 th read: ICW1 for controller 2 9 th read: ICW2 for controller 2 10 th read: ICW3 for controller 2 11 th read: ICW4 for controller 2 12 th read: OCW1 for controller 2 13 th read: OCW2 for controller 2 14 th read: OCW3 for controller 2 PIC: 21h R In service register for PIC 1 In service register for PIC 1 PIC: A0h R Interrupt request register for PIC 2 Interrupt request register for PIC 2 PIC: A1h R In service register for PIC 2 In service register for PIC 2 NMIDIS. NMI disable. Read only. This provides read access to RTC70[NMIDIS]. P92FR. Port 92 fast reset. Read-write. 1=Writes that attempt to set PORT92[0]—the fast CPU reset bit—are enabled. 0=Writes to PORT92[0] are ignored. MBL. Must be low. Read-write. This bit is required to be low at all times; otherwise undefined behavior will result. |
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