AMD-766AC datasheet(75/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PM2A Global SMI Enable Register

IO mapped (base pointer: C3A58); offset: 2B-2Ah. Default: 0000h. Read-write.

Each of the bits in this register enable SMI# interrupts for the specified status register. For each of these bits:

1=Enable the specified event to generate an SMI interrupt, regardless as to the state of PM04[SCI_EN].

Reserved

RISMI_EN

SLPBTN_EN

PWRBTN_EN SMBUS_EN

THMSMI_EN EXTSMI_EN

PMESMI_EN

765

43210

SWISMI_EN

BIOSSMI_EN SITSMI_EN

USBSMI_EN

GPIOSMI_EN PM1SMI_EN

TCO_EN

TRPSMI_EN

TRPSMI_EN. Hardware trap SMI enable. An SMI is generated if PM28[TRP_EVT] is asserted.

TCO_EN. TCO SMI interrupt enable. An SMI is generated if PM28[TCO_EVT] is asserted. Note: If

PM48[NMI2SMI_EN] is set, then PM44[NMI2SMI_STS] generates SMI interrupts regardless of the state of this bit.

Even if the TCO_EN bit is 0, NMIs are still routed to generate SMI interrupts.

PM1SMI_EN. Power management 1 SMI enable. An SMI is generated if PM28[PM1_EVT] is asserted.

GPIOSMI_EN. GPIO interrupt SMI enable. An SMI is generated if PM28[GPIO_EVT] is asserted.

USBSMI_EN. USB transfer or resume event enable. An SMI is generated if any of PM24[4:0] is asserted while

being enabled by the corresponding bits in PM25[4:0].

SITSMI_EN. System inactivity timer time out SMI enable. An SMI is generated if PM20[SIT_STS] is asserted.

BIOSSMI_EN. BIOS SMI enable. An SMI is generated if PM28[BIOS_STS] is asserted.

SWISMI_EN. Software SMI enable. An SMI is generated if PM28[SWI_STS] is asserted.

PMESMI_EN. PME# pin SMI enable. An SMI is generated if PM20[PME_STS] is asserted.

EXTSMI_EN. External SMI pin SMI enable. An SMI is generated if PM20[EXTSMI_STS] is asserted.

THMSMI_EN. THERM# pin SMI enable. An SMI is generated if PM20[THERM_STS] is asserted.

SBUS_EN. SMBus event enable. An SMI is generated if PM28[SMBUS_EVT] goes high.

PWRBTN_EN. PWRBTN# pin SMI enable. An SMI is generated if PM00[PWRBTN_STS] is asserted.

SLPBTN_EN. SLPBTN# pin SMI enable. An SMI is generated if PM00[SLPBTN_STS] is asserted.

RISMI_EN. RI# pin SMI enable. An SMI is generated when PM20[RI_STS] is asserted.

PM2C: Global SMI Control Register

IO mapped (base pointer: C3A58); offset: 2D-2Ch. Default: 0000h.

15:6

5432

Reserved

SMIACT

SMILK

EOS

Reserved

BIOS_RLS SMI_EN

SMI_EN. SMI enable control. Read-write. 1=Enable SMI generation. 0=SMI disabled (however, if SMIACT is set

and SMI_EN is cleared, then SMI# remains asserted until SMIACT is cleared).

BIOS_RLS. BIOS SCI/SMI lock release. Read; write 1 only; cleared by hardware. 1=The SCI/SMI lock has been

released. When this bit is set high, PM00[GBL_STS] is set high by the hardware. BIOS_RLS is cleared by the

hardware when PM00[GBL_STS] is cleared by software. Note that if PM02[GBL_EN] is set, then setting this bit

generates an SCI interrupt.

EOS. End of SMI. Write 1 only. Writing a 1 to this bit forces the SMI# pin to be deasserted for 4 PCI clocks. This

bit always reads as a 0.

SMILK. SMI lock control. Read-write. 1=The SMI# pin is locked into the active state after it is asserted. The

latch is controlled by SMIACT. 0=The SMI# pin is not internally latched.

SMIACT. SMI active. Read; set by hardware; write 1 to clear. This bit is set high by the hardware on the asserting

edge of SMI#. If SMILK is high, then SMIACT holds the SMI# pin in the active state. If SMILK is low, then

SMIACT has no effect on the SMI# pin.

PM2F: Software SMI Trigger Register

IO mapped (base pointer: C3A58); offset: 2Fh. Default: 00h. Read-write.

7:0

SMI_CMD

SMI_CMD. SMI command. Writes to this register set PM28[SWI_STS]. Reads of this register provide the data

last written to it. Note: This register is identically accessible from offset 1Eh as well (PM1E).

AMD-766AC Datasheet(PDF) 75 Page - Advanced Micro Devices

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