AMD-766AC datasheet(44/96 Pages) AMD

44 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

5.3.2

Legacy DMA Controller (DMAC) Registers

The legacy DMA controller (DMAC) in the IC supports the features required by the LPC I/F Specification Revision

1.0, which are a subset of the features in legacy DMA Controllers. Single, demand, verify, and increment modes are

supported. Block, decrement, cascade modes are not supported. Also, memory-to-memory transfers and external

EOPs (end of process) are not supported.

There are 7 supported DMA channels. Channels 0-3 support 8-bit transfers. Channels 5-7 support 16-bit transfers.

There is no support for 32-bit DMA transfers. LPC master device requests are made using channel 4.

Although not all registers of legacy DMA controllers are supported, the IO address locations for the unsupported

registers is consistent with legacy logic. The implemented DMAC registers are listed in the following table.

Name

Size

Number

Comments

Base Address Registers

16 bits

1 for each channel (0-7) (see note 1)

Base Word Count Registers

16 bits

1 for each channel (0-7) (see note 1)

Current Address Registers

16 bits

1 for each channel (0-7) (see note 1)

Current Word Count Registers

16 bits

1 for each channel (0-7) (see note 1)

Status Registers

8 bits

1 for Master and 1 for Slave DMAC

Command Registers

1 bit

1 for Master and 1 for Slave DMAC

Mode Registers

5 bits

1 for each channel (0-7) (see note 1)

Mask Registers

4 bits

1 for Master and 1 for Slave DMAC

Note 1: although channel 4 base and current registers exist for compatibility, they are not used.

Note that not all bits in the command and mode registers of legacy DMA controllers are implemented in the IC’s

DMA controller. The bit usage for these registers are as follows.

Command registers (master and slave DMAC)

Bit

Legacy DMAC function

DMAC function of the IC

DACK sense

Obsolete

DREQ sense

Obsolete

Late/Extended write

Obsolete

Fixed/Rotating priority

Obsolete (always fixed priority)

Normal/Compressed timing

Obsolete

Controller enable/disable

Ch0 address hold enable/disable

Obsolete

Memory-to-memory enable/disable

Obsolete

Mode registers (master and slave DMAC)

Bit

Legacy DMAC function

DMAC function of the IC

7:6

00b Demand mode select

01b Single mode select

10b Block mode select

11b Cascade mode select

00b Demand mode select

01b Single mode select

10b Obsolete

11b Obsolete (see note)

Address increment/decrement select

Obsolete (always increment)

Auto initialization enable/disable

Auto initialization

enable/disable

3:2

00b Verify transfer

01b Write transfer

10b Read transfer

11b Illegal

00b Verify transfer

01b Write transfer

10b Read transfer

11b Illegal

1:0

Channel select

Note: DMA channel 4 is hard-wired into cascade mode; however cascade mode is obsolete for all other channels.

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