AMD-766AC datasheet(73/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PM24: LPT-USB Event Status Register

IO mapped (base pointer: C3A58); offset: 24h. Default: 00h. Read; set by hardware; write 1 to clear.

765

321

LPT3_STS

LPT2_STS

LPT1_STS

USB_RSM_STS

USB_BLK_STS USB_INT_STS

USB_ISO_STS USB_CTL_STS

USB_CTL_STS. USB control transfer status. 1=A USB control transfer has been completed.

USB_ISO_STS. USB isochronous transfer status. 1=A USB isochronous transfer has been completed.

USB_INT_STS. USB interrupt transfer status. 1=A USB interrupt transfer has completed.

USB_BLK_STS. USB bulk transfer status. 1=A USB bulk transfer has been completed.

USB_RSM_STS. USB-defined resume event status. Access to this bit is replicated in PM20; see that register. This

bit resides on the VDD_AUX power plane.

LPT1_STS. IO access to 378-37Fh status. 1=An access to IO space between 378h and 37Fh has occurred.

LPT2_STS. IO access to 278-27Fh status. 1=An access to IO space between 278h and 27Fh has occurred.

LPT3_STS. IO access to 3BC-3BFh status. 1=An access to IO space between 3BCh and 3BFh has occurred.

PM25: LPT-USB Event Interrupt Enable Register

IO mapped (base pointer: C3A58); offset: 25h. Default: 0000h. Read-write.

For each of the bits in this register: 1=Enable a corresponding status bit in PM24 to generate an SMI or SCI

interrupt (based on the state of PM04[SCI_EN]); 0=Do not enable the SMI or SCI interrupt.

765

43210

LPT3_EN

LPT2_EN

LPT1_EN

USB_RSM_EN

USB_BLK_EN

USB_INT_EN

USB_ISO_EN

USB_CTL_EN

USB_CTL_EN. USB control transfer interrupt enable.

USB_ISO_EN. USB isochronous transfer interrupt enable.

USB_INT_EN. USB interrupt transfer interrupt enable.

USB_BLK_EN. USB bulk transfer interrupt enable.

USB_RSM_EN. USB-defined resume event interrupt enable. Access to this bit is replicated in PM22.

LPT1_STS. IO access to 378-37Fh interrupt enable.

LPT2_STS. IO access to 278-27Fh interrupt enable.

LPT3_STS. IO access to 3BC-3BFh interrupt enable.

PM26: Sleep State Resume Enable Register

IO mapped (base pointer: C3A58); offset: 27-26h. Default: 2200h. Read-write.

The CTL bits in this register enable resume events from STR, STD, and SOFF. This register resides on the

VDD_AUX power plane.

Reserved

RI_CTL

SBOR_DIS

SLPBTN_CTL

PBOR_DIS

PME_CTL

PB_CTL

RTC_PS_CTL

765

43210

Reserved

HSLV_CTL

SNP_CTL

USBRSM_CTL

EXTSMI_CTL

EXTSMI_CTL. EXTSMI# resume. 1=Enables the assertion of PM20[EXTSMI_STS] to resume the system from

STR, STD, and SOFF.

USBRSM_CTL. USB resume. 1=Enables the assertion of PM20[USB_RSM_STS] to resume the system from STR,

STD, and SOFF.

SNP_CTL. SMBus snoop address match resume. 1=Enables the assertion of PME0[SNP_STS] to resume the

system from STR, STD, and SOFF.

HSLV_CTL. SMBus host-as-slave address match resume. 1=Enables the assertion of PME0[HSLV_STS] to

resume the system from STR, STD, and SOFF.

RTC_PS_CTL. Real time clock resume. 1=Enables the assertion of PM00[RTC_STS] to resume the system from

STR, STD, and SOFF.

PB_CTL. Power button resume. 1=Enables the assertion of PM00[PWRBTN_STS] to resume the system from STR,

STD, and SOFF.

PME_CTL. PME# resume. 1=Enables the assertion of PM20[PME_STS] to resume the system from STR, STD,

and SOFF.

AMD-766AC Datasheet(PDF) 73 Page - Advanced Micro Devices

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