AMD-766AC datasheet(41/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

Accesses to BIOS space in the low megabyte (between 000C_0000h and 000F_FFFFh) are mapped to the top

megabyte (between FFFC_0000h and FFFF_FFFFh) on the LPC bus; the OAR locks for these—whether the LPC bus

or ISA bus is targeted—apply to these accesses based on the remapped address at the top megabyte. Note: There is

an additional OAR lock specified in C0A8C. Note: OAR locks only apply to BIOS address space; if there is an

access to an OAR lock address range that is not in BIOS address space as specified by C0A43, then the OAR lock

PCI special cycles determine when the system is in SMM mode, for the SMM-mode locks. The special cycles data

phase determines the system state as follows:

0005_0002h: system is entering SMM mode;

0006_0002h: system is exiting SMM mode.

C0A88:

31:28

27:24

23:20

19:16

15:12

11:8

7:4

3:0

OARE

OARC

OARA

OAR8

OAR6

OAR4

OAR2

OAR0

C0A84:

31:28

27:24

23:20

19:16

15:12

11:8

7:4

3:0

OARF

OARE

OARD

OARC

OARB

OARA

OAR9

OAR8

C0A80:

31:28

27:24

23:20

19:16

15:12

11:8

7:4

3:0

OAR7

OAR6

OAR5

OAR4

OAR3

OAR2

OAR1

OAR0

OARx[0], RDLOCK. BIOS sector x read lock. Read; write if enabled by SLLOCK and FLLOCK. 0=Read access

to BIOS sector x enabled. 1=Read access to BIOS sector x disabled.

OARx[1], WRLOCK. BIOS sector x write lock. Read; write if enabled by SLLOCK and FLLOCK. 0=Write

access to BIOS sector x enabled (if C0A40[RWR]=1). 1=Write access to BIOS sector x disabled.

OARx[2], SLLOCK. SMM access to RD/WRLOCK lock. Read; write 1 only. This bit may only be set high by

software; it is cleared by PCIRST#. 0=Read-write access to RDLOCK and WRLOCK enabled (if FLLOCK=0).

1=Write access to RDLOCK and WRLOCK only enabled in SMM mode (if FLLOCK=0).

OARx[3], FLLOCK. Full access to RD/WRLOCK lock. Read; write 1 only. This bit may only be set high by

software; it is cleared by PCIRST#. 0=Read-write access to RDLOCK and WRLOCK enabled. 1=Write access to

RDLOCK and WRLOCK disabled (whether the system is in SMM mode or not).

C0A8C: OAR Control Register

Configuration space; function 0; offset: 8Ch. Default: 0000_0000h.

543:0

Reserved

LKLOCK

OAR_ROB

OAR_ROB. OAR locks for rest of BIOS space. Read-write. These four bits are defined identically to the OAR

registers in C0A80/84/88. They apply to the BIOS ROM space across [FFEF_FFFFh:FFC0_0000h] (if the space is

specified by C0A43 to be BIOS).

LKLOCK. SMM access to the ROM access registers lock. Read; write 1 only. This bit may only be set high by

software; it is cleared by PCIRST#. 0=Write access to C0A80/C084/C0A88/C0A8C and C0A43 always enabled.

1=Write access to C0A80/C084/C0A88/C0A8C and C0A43 only enabled in SMM mode (see C0A80 for

determination of when the system is in SMM mode).

AMD-766AC Datasheet(PDF) 41 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 41 Page - Advanced Micro Devices

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