AMD-766AC datasheet(84/96 Pages) AMD

84 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PMD8: GPIO Pin Interrupt Enable Register

IO mapped (base pointer: C3A58); offset: DB-D8h. Default: 0000_0000h. Read-write.

For each of these bits: 1=Enable either an SCI or SMI interrupt based on the state of PM04[SCI_EN] if the

corresponding status bit in PMD4 is set. Note: If C3A42[GPIOSCI] is low, these SCI/SMI interrupts are disabled.

However, if PM2A[GPIOSMI_EN] is high, an SMI is generated regardless of the state of C3A42[GPIOSCI].

31:0

GPIO IRQ enable bits

PMDC: GPIO Output Clock 0 and 1 Register

IO mapped (base pointer: C3A58); offset: DF-DCh. Default: FFFF_FFFFh. Read-write.

This register specifies the high time and the low time for the GPIO output clocks. These clocks may be selected as

the output for any of the GPIO pins. These output clocks consist of a 7-bit down counter that is alternately loaded

with the high time and the low time. The clock for the counters is selected by CLK[1,0]BASE.

31:30

29:23

22:16

15:14

13:7

6:0

CLK1BASE CLK1HI

CLK1LO

CLK0BASE CLK0HI

CLK0LO

CLK[1:0]LO. GPIO output clock 0 and 1 low time. Specifies the low time for the GPIO output clocks in

increments of the clock period specified by CLK[1,0]BASE (e.g., if the base is 16 milliseconds, then 0 specifies 16

milliseconds, 1 specifies 32 milliseconds, etc.). CLK0LO specifies the low time for GPIO output clock 0 and

CLK1LO specifies the low time for GPIO output clock 1.

CLK[1:0]HI. GPIO output clock 0 and 1 high time. Specifies the high time for the GPIO output clocks in

increments of the clock period specified by CLK[1,0]BASE (e.g., if the base is 16 milliseconds, then 0 specifies 16

milliseconds, 1 specifies 32 milliseconds, etc.). CLK0HI specifies the high time for GPIO output clock 0 and

CLK1HI specifies the high time for GPIO output clock 1.

CLK[1:0]BASE. GPIO output clock timer base. Specifies the clock for the counter that generates the GPIO output

clock. 00b specifies a clock period of 250 microseconds; 01b specifies a clock period of 2 milliseconds; 10b specifies

a clock period of 16 milliseconds; and 11b specifies a clock period of 128 milliseconds. CLK0BASE specifies the

clock for GPIO output clock 0 and CLK1BASE specifies the clock for GPIO output clock 1.

PME0: SMBus Global Status Register

IO mapped (base pointer: C3A58); offset: E1-E0h. Default: 0000h.

Some of these bits have the ability to generate an SCI/SMI interrupt, if they are enabled to do so in PME2.

Reserved

SMB_BSY

SMBA_STS HSLV_STS

SNP_STS

765

43210

Reserved

TO_STS

HCYC_STS HST_BSY

PRERR_STS COL_STS

ABRT_STS

ABRT_STS. Host transfer abort status. Read; set by hardware; write 1 to clear. 1=A host transfer was aborted by

the PME2[ABORT] command.

COL_STS. Host collision status. Read; set by hardware; write 1 to clear. 1=A host transfer was attempted while

the SMBus was busy.

PRERR_STS. Protocol error status. Read; set by hardware; write 1 to clear. 1=A slave device did not generate an

acknowledge at the appropriate time during a host SMBus cycle.

HST_BSY. Host controller busy. Read only. 1=The SMBus host controller is currently busy with a cycle.

HCYC_STS. Host cycle complete status. Read; set by hardware; write 1 to clear. 1=A host cycle completed

successfully.

TO_STS. Time out error status. Read; set by hardware; write 1 to clear. 1=A slave device forced a time out by

holding the SMBUSC pin low for more than 30 milliseconds.

SNP_STS. Snoop address match status. Read; set by hardware; write 1 to clear. 1=An SMBus master (including

the host controller) generated an SMBus cycle with a 7-bit address that matched the one specified by PMEF. This bit

is not set until the end of the acknowledge bit after the last byte is transferred over the SMBus cycle; if a time out

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