AMD-766AC datasheet(77/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

PM41: TCO Timer Initial Value Register

IO mapped (base pointer: C3A58); offset: 41h. Default: 04h. Read-write.

7:6

5:0

Reserved

TCOTIME

TCOTIME. TCO timer reload value. Specifies the value loaded into the TCO timer; see PM40.

PM42: TCO SMI Data In Register

IO mapped (base pointer: C3A58); offset: 42h. Default: 00h. Read-write.

7:0

TCOSMI

TCOSMI. TCO SMI data. Writes of any value to this register set PM44[SW_TCO_SMI] and generate an SMI.

Reads provide the last value written.

PM43: TCO SMI Data Out Register

IO mapped (base pointer: C3A58); offset: 43h. Default: 00h. Read-write.

7:0

TCOOUT

TCOOUT. TCO output data to OS. Writes of any value to this register set PM44[TCO_INT_STS] and generate an

IRQ as specified by C3A44[TCO_INT_SEL] and PM22[TCOSCI_EN]. Reads provide the last value written.

PM44: TCO Status 1 Register

IO mapped (base pointer: C3A58); offset: 45-44h. Default: 0000h. Read; set by hardware; write 1 to clear.

Reserved

IBIOS_STS

765

43210

Reserved

TOUT_STS

TCO_INT_STS SW_TCO_SMI

NMI2SMI_STS

NMI2SMI_STS. NMI to SMI status. 1=An NMI was detected while PM48[NMI2SMI_EN] was high. This bit is

not affected by setting PM48[NMI_NOW]. Assertion of this bit results in an SMI interrupt.

SW_TCO_SMI. Software-generated SMI status. 1=A write to PM42 was detected. This bit may be enabled by

PM2A[TCO_EN] to generate SMI interrupts.

TCO_INT_STS. TCO interrupt status. 1=A write to PM43 was detected. Assertion of this bit results in an IRQ as

specified by C3A44[TCO_INT_SEL] and PM22[TCOSCI_EN].

TOUT_STS. TCO timer timeout status. 1=The TCO timer, PM40, counted past zero. This bit may be enabled by

PM2A[TCO_EN] to generate SMI interrupts.

IBIOS_STS. BIOS illegal access status. 1=An illegal access to BIOS address space has occurred. This occurs

when: (1) there is a read to a read-locked address or a write to a write-locked address as specified by C0A40[RWR],

C0A80, C0A84, C0A88, and C0A8C[3:0] or (2) C0A40[BLE]=1 and C0A40[RWR] is written from a 0 to a 1. This

bit may enabled by PM2A[TCO_EN] to generate SMI interrupts.

PM46: TCO Status 2 Register

IO mapped (base pointer: C3A58); offset: 46h. Default: 00h. Read; set by hardware; write 1 to clear.

765

43210

Reserved

BOOT_STS

2NDTO_STS

INTRDR_STS

INTRDR_STS. Intruder detect status. 1=The INTRUDER# pin was detected asserted for more than 60

microseconds (debounce time). This register resides on the VDD_AL power plane. It functions in all power states

unless VDD_AL is not valid. When VDD_AL is powered, this bit defaults low.

2NDTO_STS. Second TCO time out status. 1=The TCO timer, PM40, timed out a second time before

PM44[TOUT_STS] was cleared. If enabled by C3A41[NO_REBOOT], assertion of this bit reboots the system. This

bit resides on the VDD_AUX power plane.

BOOT_STS. Boot status. 1=The TCO timer has timed out twice without any BIOS ROM accesses. This is detected

when PM46[2NDTO_STS] changes from 0 to 1 after any PCIRST# before any BIOS ROM accesses have occurred.

This bit resides on the VDD_AUX power plane.

AMD-766AC Datasheet(PDF) 77 Page - Advanced Micro Devices

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