AMD-766AC datasheet(45/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

5.3.3

Legacy Programmable Interval Timer (PIT) Registers

These timers are halted from counting, if enabled to do so in C3A4C[PIT_DIS], when PRDY is asserted.

The following are ports used to access the legacy PIT:

Offset

Access Port

40h

Write

Counter 0 write access port

Read

Counter 0 read access port

41h

Write

Counter 1 access port

Read

Counter 1 read access port

42h

Write

Counter 2 access port

Read

Counter 2 read access port

43h

Write

Control byte

Read

Not supported

PORT43: PIT Control Byte Register

Fixed IO space; offset: 43h. Default: 00h. Write only.

Bits

Description

7:6

SC[1:0]: select counter. Specifies the counter that the command applies to as follows:

00b

Counter 0.

01b

Counter 1.

10b

Counter 2.

11b

Read back command.

5:4

RW[1:0]: read-write command. Specifies the read-write command as follows:

00b

Counter latch command.

01b

Read/write least significant byte only.

10b

Read/write most significant byte only.

11b

Read/write least significant byte followed by most significant byte.

3:1

M[2:0]: counter mode. Specifies the mode in which the counter selected by SC[1:0] operates as follows:

000b Interrupt on terminal count.

001b Hardware retriggerable one-shot (not supported).

010b Rate generator.

011b Square wave mode.

100b Software triggered strobe.

101b Hardware triggered (retriggerable) strobe (not supported).

110b When this value is written, 010b is stored in the register, rate generator mode.

111b When this value is written, 011b is stored in the register, square wave mode.

BCD: binary coded decimal. 1=Counter specified by SC[1:0] operates in binary coded decimal. 0=Counter

specified by SC[1:0] operates in 16-bit binary mode.

AMD-766AC Datasheet(PDF) 45 Page - Advanced Micro Devices

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