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AMD-766AC Datasheet(PDF) 46 Page - Advanced Micro Devices |
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AMD-766AC Datasheet(HTML) 46 Page - Advanced Micro Devices |
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46 / 96 page  Preliminary Information 23167B – March 2001 AMD-766 TM Peripheral Bus Controller Data Sheet 46 5.3.4 Legacy Programmable Interrupt Controller (PIC) Registers The legacy programmable interrupt controller (PIC) includes a master, which is accessed through ports 20h and 21h and controls IRQ[7:0], and a slave, which is accessed through ports A0h and A1h and controls IRQ[15:8]. The following are all the PIC registers. Offset Access type Register 20h (master), Write only; D[4]=1b Initialization command word 1 (ICW1) A0h (slave) Write only; D[4:3]=00b Operation command word 2 (OCW2) Read-write; D[4:3]=01b Operation command word 3 (OCW3) 21h (master), Write only Initialization command word 2 (ICW2) A1h (slave) Write only Initialization command word 3 (ICW3) Write only Initialization command word 4 (ICW4) Read-write Operation command word 1 (OCW1) D[4:3] above refers to bits[4:3] of the associated 8-bit data field. Normally, once ICW1 is sent, ICW2, ICW3, and ICW4 are sent in that order before any OCW registers are accessed. ICW1: Initialization Command Word 1 Register Fixed IO space; offset: 20h for master and A0h for slave; data bit[4] must be high. Write only. Bits Description 7:5 A[7:5]: interrupt vector address. These bits are not implemented. 4 This should always be high. 3 LTIM: level triggered mode. This bit is not implemented; PORT4D0 controls this function instead. 2 ADI: call address interval. This bit is not implemented. 1 SNGL: single mode. This bit must be programmed low to indicate cascade mode. 0 IC4: ICW4 needed. This bit must be programmed high. ICW2: Initialization Command Word 2 Register Fixed IO space; offset: 21h for master and A1h for slave. Write only. ICW3M: Initialization Command Word 3 for Master Register Fixed IO space; offset: 21h. Write only. Bits Description 7:0 SLAVES[7:0]. These bits must always be programmed to 04h. ICW3S: Initialization Command Word 3 for Slave Register Fixed IO space; offset: A1h. Write only. Bits Description 7:3 Reserved (must be programmed to all zeros). 2:0 ID[2:0]. These bits must always be programmed to 02h. ICW4: Initialization Command Word 4 Register Fixed IO space; offset: 21h for master and A1h for slave. Write only. Bits Description 7:5 Reserved (must be programmed all zeros) 4 SFNM. Special fully nested mode. This bit is normally programmed low. 3:2 BUFF and MS. These two are normally programmed to 00b for non-buffered mode. 1 AEOI. Auto EOI. This bit is ignored; the IC only operates in normal EOI mode (this bit low). 0 UPM. x86 mode. This bit is ignored; the IC only operates in x86 mode (this bit high). |
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