AMD-766AC datasheet(47/96 Pages) AMD

47 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

OCW1: Operation Command Word 1 Register

Fixed IO space; offset: 21h for master and A1h for slave. Write only.

Bits

Description

7:0

MASK[7:0]. Interrupt mask. 1=Interrupt is masked. Masking IRQ2 on the master interrupt controller

masks all slave-controller interrupts.

OCW2: Operation Command Word 2 Register

Fixed IO space; offset: 20h for master and A0h for slave; data bits[4:3] must be 00b. Write only.

Bits

Description

7:5

R (bit 7), SL (bit 6), and EOI (bit 5). These are decoded as:

R, SL, EOI Function

000b

* Rotate in auto EOI mode clear.

100b

* Rotate in auto EOI mode set

001b

Non-specific EOI mode.

101b

Rotate on non-specific EOI command

010b

No operation.

110b

** Set priority command

011b

Specific EOI command.

111b

** Rotate on specific EOI command

Not supported.

Uses IRLEVEL field.

4:3

Reserved (must be programmed all zeros).

2:0

IRLEVEL. Interrupt request level. Specifies the interrupt request level to be acted upon.

OCW3: Operation Command Word 3 Register

Fixed IO space; offset: 20h for master and A0h for slave; data bits[4:3] must be 01b. Write only.

Bits

Description

Must be programmed low.

6:5

ESMM (bit 6) and SMM (bit 5). Special mask mode. These are decoded as:

[ESMM, SMM] = 0Xb

No action.

[ESMM, SMM] = 10b

Reset special mask mode.

[ESMM, SMM] = 11b

Set special mask mode.

4:3

01b

P: poll command. 1=Poll enabled; next IO read of the interrupt controller treated like an interrupt

acknowledge cycle.

1:0

RR (bit 1) and RIS (bit 0). Read register command. These are decoded as:

[RR,RIS] = 0Xb

No action.

[RR,RIS] = 10b

Read in-request (IR) register.

[RR,RIS] = 11b

Read IS register.

AMD-766AC Datasheet(PDF) 47 Page - Advanced Micro Devices

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