AMD-766AC datasheet(40/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

ASIO. Alternate super IO configuration. 1=Alternate super IO configuration IO ports, 4Eh - 4Fh, are routed to the

LPC bus. 0=These accesses are routed to the ISA bus.

C0A55: LPC Bus Decode Register 4

Configuration space; function 0; offset: 55h. Default: 00h. Read-write.

7:5

3:0

Reserved

GP1EN

GP1RANGE

GP1RANGE. Game port 1 range. Selects one byte of IO address space in the range 200h - 20Fh (where

GP1RANGE specifies the four LSBs of the address) that is routed to the LPC bus.

GP1EN. Game port 1 enable. 1=Game port 1 accesses specified by the GP1RANGE field in this register are routed

to the LPC bus. 0=These accesses are routed to the ISA bus.

C0A56: LPC Bus Decode Register 5

Configuration space; function 0; offset: 56h. Default: 00h. Read-write.

7:5

3:0

Reserved

GP2EN

GP2RANGE

GP2RANGE. Game port 2 range. Selects one byte of IO address space in the range 200h - 20Fh (where

GP2RANGE specifies the four LSBs of the address) that is routed to the LPC bus.

GP2EN. Game port 2 enable. 1=Game port 2 accesses specified by the GP2RANGE field in this register are routed

to the LPC bus. 0=These accesses are routed to the ISA bus.

C0A58: LPC Bus Generic IO Decode Register

Configuration space; function 0; offset: 5B-58h. Default: 0000_DE01h. Read-write.

31:16

15:9

8:0

Reserved

IOBASE

Reserved

IOBASE. Generic IO base address. Specifies bits [15:9] of the base address for a 512-byte generic IO address range

that is routed to the LPC bus. This function is disabled if IOBASE is set to 00h.

C0A5C: LPC Bus Generic Memory Decode Register

Configuration space; function 0; offset: 5F-5Ch. Default: 0000_0000h. Read-write.

31:20

19:0

MEMBASE

Reserved

MEMBASE. Generic memory base address. Specifies bits [31:20] of the base address for a 1-megabyte generic

memory address range that is routed to the LPC bus. This function is disabled if MEMBASE is set to 000h.

C0A70: Device and Subsystem ID Read-Write Register

Configuration space; function 0; offset: 73-70h. Default: 0000_0000h. Read-write.

31:16

15:0

SSID

SSVENDORID

SSVENDORID and SSID. Subsystem vendor ID and Subsystem ID. The value placed in this register is visible in

C0A2C, C1A2C, C3A2C, and C4A2C.

C0A80/C0A84/C0A88: BIOS Access Control Register

Configuration space; function 0; offset: 8B-80h. Default: 0000_0000h. Read-write. These registers include 24 4-bit

registers called OAR (open at reset) locks. Each 4-bit register applies to a sector of the BIOS in the 5 megabyte

BIOS range at the top of the 4-gigabyte address space as follows:

C0A84 and C0A80 include 16 four-bit lock registers, OARx where x ranges from 0h to Fh; each four-bit register

controls a 64Kbyte address range at the top megabyte of memory as follows: [FFF(x)_FFFFh: FFF(x)_0000h].

C0A88 includes 8 four-bit lock registers, OARx where x ranges as [E, C, A, 8, 6, 4, 2, 0]; each four-bit register

controls an 8Kbyte address range as follows: [FFBF_(x+1)FFFh: FFBF_(x)000h].

AMD-766AC Datasheet(PDF) 40 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 40 Page - Advanced Micro Devices

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