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UPD9971 Datasheet(PDF) 33 Page - Renesas Technology Corp

Part # UPD9971
Description  MOS INTEGRATED CIRCUIT
PDF  112 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD9971 Datasheet(HTML) 33 Page - Renesas Technology Corp

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µPD9971
Data Sheet S17455EJ2V0DS
31
4. MUSIC SERIAL INTERFACE
4.1 Audio Serial Interface (ASIO)
When LRCLK = 0 in the SEL_ASI register, L-ch data is assigned during the high-level period of LRCLK and R-ch
data is assigned during the low-level period of LRCLK. For IIS format, this is reversed, in which case LRCLK =1 should
be set.
Within each of these periods, the format can be switched among right justified, left justified, and IIS format.
Selection of master mode or slave mode is also enabled. The number of data bits per frame can be set via the BFS
[4:0] bits in the SEL_FS register. The serial input/output timing is shown below.
Figure 4-1 Audio Serial Interface Timing
(a) Right-Justified Format
LRCLK
BCLK
ASO
ASI
1/fs
Lch
Rch
D2
D1 D0
D15 D14
D2
D1 D0
D15 D14
D2
D1 D0
D2
D1 D0
D15 D14
D15 D14
D2
D1 D0
D2
D1 D0
(b) Left-Justified Format
LRCLK
BCLK
ASO
ASI
1/fs
Lch
Rch
D1 D0
D15 D14
D2
D1 D0
D15 D14
D2
D1 D0
D2
D1 D0
D15 D14
D15 D14
D1 D0
D2
D1 D0
D15 D14
D15 D14
(c) IIS Format
LRCLK
BCLK
ASO
ASI
1/fs
Lch
Rch
D1 D0
D15 D14
D1 D0
D15 D14
D1 D0
D1 D0
D15 D14
D15 D14
D1 D0
D1 D0
D15
D15



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